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How to model simple level shifter circuit
Benta, thanks for the tip. I will look into ATE Pin Driver ICs. From a brief glance at one of the datasheets it looks like they require a serial interface and a lot of control signals, and they are designed for -1.5 to 6.0V operation. Not sure if this is the answer for this particular...- joshxdr
- Post #15
- Forum: Circuit design
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How to model simple level shifter circuit
The coax cable is 1.5 meter 50ohm cable. The through-hole pins on the level translator will tend to filter out high frequency. There are similar bandwidth limiters on the DUT side (connectors and/or wafer probes). In theory it is possible to generate reflections, but using this kind of...- joshxdr
- Post #12
- Forum: Circuit design
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How to model simple level shifter circuit
The signal travels from the level shifter to an IC being tested. CMOS input buffers. Sometimes through a probecard to a wafer. Sometimes to a packaged IC.- joshxdr
- Post #10
- Forum: Circuit design
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How to model simple level shifter circuit
I don't care if the level shifter has 1ns delay or 20ns delay. I can compensate for that with the calibration feature of my tester. I can't compensate for a delta between rising edge and falling edge. The delta is what I am trying to minimize.- joshxdr
- Post #8
- Forum: Circuit design
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How to model simple level shifter circuit
From the datasheet: Table 5. TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; VEE = ?5.5 V to ?3.0 V; GND = 0.0 V; TA = ?40°C to 85°C Symbol Characteristic Condition Min Typ Max Unit VOH Output HIGH Voltage IOH = ?3.0 mA 2.2 V VOL Output LOW Voltage IOL = 24 mA 0.5 V For pulldown it can sink 24mA...- joshxdr
- Post #7
- Forum: Circuit design
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How to model simple level shifter circuit
The output of this device is NOT 24mA. I am shifting to 5 to 8.3v. My vee is 0 and my vss is 5v and vdd is 8.3. That is a 3.3v swing. If you actually read the datasheet, the Vol and Voh numbers show how assymetrical the drive is. The major source of parasitic cap in my circuit is the thru...- joshxdr
- Post #6
- Forum: Circuit design
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How to model simple level shifter circuit
I would like the rising edge delay to match the falling edge delay within 2 ns. I would like to know if adding a buffer would make this better or worse.- joshxdr
- Post #3
- Forum: Circuit design
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How to model simple level shifter circuit
I am building a level shifter circuit for digital signals. It is part of a digital circuit test system. Input signal comes in by coax cable to a pair of 0.1" header pins using z-trace connector. Output signal is also uses coax cable connected to a pair of 0.1" header pins with z-trace...- joshxdr
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- Replies: 14
- Forum: Circuit design
