> With the pull-down at 10k, a high on the FPGA pin shows
> up as half-voltage at the base of the transistor... a
> 3.3V FPGA will drive the transistor base to 1.65V
> (actually, a bit less considering the amount of current
> into the base of the transistor).
Good point, the MMBT3904...
> I'd make the pull-down 100k (assuming the pin's leakage
> current is okay with that).
Could you be more descriptive? Why would you make the
pull-down 100k instead of 10K?
Thanks!
Thanks for all the input, I included a circuit diagram in case anyone else finds themselves down the same path :-)
I added a 10K pull-down from the base to cover FPGA reset, where the IO pin floats. As suggested, I used a 10K resistor between the 3.3V FPGA output and the 2N3904 NPN base to set...
Hello,
Goal: Drive a cep_2242 piezo buzzer from a 3.3V FPGA output. Driving direct from FPGA does not generate the required sound volume, not surprising considering the buzzer operating voltage is 3-16 Vdc (7mA max at 12V).
I would like to use an integrated load switch, so I can provide 12V to...
