Hi,
On the process I am working on the minimum gate-length is
0.6um. I need a transistor of dimension 60/0.2.
I am thinking that if I stack three 60/0.6 in parallel I
will get an equivalent transitor of 180/0.6 or 60/0.2. Is
this a valid assumption??
Thanks a million.
Dominic
Howdy,
A newbie here.
I am designing a 12bit DAC using Thin Film resistors. Current-out DAC, R2R ladder, Vdd=0->5V, Vref=0->10V. Has anyone on ythis board done one recently and if so what has the linearity been like? DNL and INL. Also what is max freq of operation (worst case).
Thanks in...