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Power dissipation in open drain CMOS
Thanks melone for your post. I thought that open drain outputs formed an AND function, and the inactive state is low. May be at an internal transistor level, it is an AND but at the board level, it makes sense that it is an OR (only one reset line needs to be active for the system to reset).- pleigh
- Post #3
- Forum: Circuit design
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Power dissipation in open drain CMOS
I was told that an open drain CMOS requires a passive pullup resistor at the output pin. But what happens when the ouput is active low? Isn't it sinking current from the pullup and inefficiently consumes power?- pleigh
- Thread
- Replies: 4
- Forum: Circuit design
