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Capacitor overvoltage formula(s) 1

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AusLee

Electrical
Sep 22, 2004
259
Hello,

Short version :)

Could you please explain the formula posted by Mr. Jhrist regarding the over voltage caused by excessive capacitance, as posted in the followin closed thread:


Long version :(

I have looked into several references, starting with the series capacitor which was easy to demonstrate, as well as the parallel correction in case the source is one of current, not voltage, however i could not find any schematic explaining the over voltage equatrion. I put all these references on the following webpage if anyone is interested in reading them:


I hope somoen will be kind enough to explain where this equation came from and thanks.
 
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I have a splitting headache right now so excuse me if I don't check all the maths, but a Google for [blue]Ferranti Effect[/blue] might shed some light on voltage rise due to capacitance on a line. I picked off one which looked reasonable from the many hits:


The linked page in your post isn't working at present so I couldn't look at the references right now. I'll look again later - off for an Ibuprofen or two now...


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Sometimes I only open my mouth to swap feet...
 
Hi Scotty,

I looked up Mr Ferranti, he was chairman of the IEC in 1911. Thank you for the link, i understand what they say, but i still hope to get the details of that above mentioned formula.

I have tried both pages linked in my OP, they both work. Please give "tripod" a little time as it is a free server and they insert one ad on top, one at the bottom of the page + 1 pop-up :)
 
Voltage drop in a circuit can be calculated by the formula:

(1) VD = I·R·cos([θ]) + I·XL·sin([θ]) where

VD is the decrease in L-G voltage magnitude in volts
I is line current in amps
R is the resistance of the line in ohms
X is the inductive reactance of the line in ohms
[θ] is the current phase angle

In terms of the percent of nominal L-G voltage,

(2) VD% = 100·VD/(1000·kV/[√]3) where

kV is the L-L voltage

In the first term of (1), I·cos([θ]) is the real component of the current and I·sin([θ]) is the reactive component.

The reactive component of the current is the inductive load current minus the capacitive current from the capacitors.

The capacitive current is

kvar/(kV·[√]3)

VD% is thus reduced by this capacitive current times the line reactance or

100·[kvar/(kV·[√]3)]·XL/(1000·kV/[√]3)
or
(kvar·XL)/(10·kV²)

 
Thank you Jghrist for the explanation.

Could you please be kind enough to clear these doubts for me please:

1. In the above formula, are R and XL the short circuit impedance of the transformer (Zcc), not the resitance and reactance of the load, nor an equiavalent impedance of the load in parallel with the transformer?

I think R and XL should indeed be Zcc // Z(load), but since the impedance of the source is usually smaller than the load, then Zcc // Z(load) = Zcc, is this right?


2. I am not clear on the following transformation used in IEEE Std 141-1993 page 400:


From your equation, and considering R<<X, dV = I * XL * sin(phi)

with, I*sin(phi) = kVAR / (kV * 1.736)

and dV% = dV * 100 / (V * 1.736)

dV% = [kVAR / (kV * 1.736)] * XL * 100 / (V * 1.736)

dV% = VAR * XL * 100 / (3 * V^2)

how do they conclude that

dV% = capacitor kVAR * %transformer impedance / transformer kVA ?

What it worse, they give an example for a 1,000 kVA trafo with Zcc = 6% and to which a 300 kVAR capacitor bank is connected, and they calculate:

dV% = 300 * 6% / 1000 = 1.8 %

They do not deduct from the 300 kVAR whatever lagging kVAR the inductance of the load may be consuming. Say the load has 200 kVAR in inductive load, then the 300 kVAR will be only 100 kVAR in excess, and the formula must be applied as follows:

dV% = 100 * 6% / 1000 = 0.6%

is that correct? I hope not because i think IEEE standards must be flawless.

3. If the capacitor is at the load, not at the transformer, then the cable is an R(cable)+L(cable) in seriers with R(load)+L(load). By neglecting the resistances, is L(cable) worth taking into account? or the fact that it is not in parallel with the capacitor does not make any sense?

Thank you again for your answers.

 
1. In the above formula, are R and XL the short circuit impedance of the transformer (Zcc), not the resitance and reactance of the load, nor an equiavalent impedance of the load in parallel with the transformer?

I think R and XL should indeed be Zcc // Z(load), but since the impedance of the source is usually smaller than the load, then Zcc // Z(load) = Zcc, is this right?
R and XL are the resistance and reactance of whatever it is you are finding the voltage drop/rise in. Either a transformer or a line or both.
how do they conclude that

dV% = capacitor kVAR * %transformer impedance / transformer kVA ?
% transformer impedance = XL·kVA/(kV²·10)

and

(% transformer impedance)/kVA = XL/(kV²·10)

Substitute into the IEEE Std 141 equation and you get

(kvar·XL)/(10·kV²)
 
What it worse, they give an example for a 1,000 kVA trafo with Zcc = 6% and to which a 300 kVAR capacitor bank is connected, and they calculate:

dV% = 300 * 6% / 1000 = 1.8 %

They do not deduct from the 300 kVAR whatever lagging kVAR the inductance of the load may be consuming. Say the load has 200 kVAR in inductive load, then the 300 kVAR will be only 100 kVAR in excess, and the formula must be applied as follows:

dV% = 100 * 6% / 1000 = 0.6%

is that correct? I hope not because i think IEEE standards must be flawless.
The equation is for the voltage rise caused by the capacitors. There will be a voltage drop caused by the load (inductive and resistive) separate from the voltage rise, given by equation (7) of IEEE Std 141.
 
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