CMOS current limiting and paralleling output 1

[homoly]

Hello,

I have been involved in modifications on the existing device using CMOS ICs with which I do not have practical experience and for this reason I would like to ask few questions.

In new circuit I would have to connect the output of LM339 with CD4013B flip flop. I have found article recommending series resistor between comparator and CMOS:

http://www.ecelab.com/interfacing-opamp-ttl-cmos.htm

.My case is Fig.1 with 12V supply. My question is about the resistor sizing why exactly the 10K value is selected? After some research I have found the upper limit of resistor value is given by a time constant of Rlim and gate&PCB tracks capacitance , that in the case of 15 VDD supply CMOS the rise time of the input signal should not exceed 4-5us to avoid output oscillations.
I assume the lower value is given by the maximum allowed input current to the gate when internal clamping diodes are activated by ESD or transient overvoltage. Here I found in datasheet

http://www.fairchildsemi.com/ds/CD/CD4013BC.pdf

only the IIN = 1uA which seems to me as the maximum current in normal operation defining input resistance quality not the maximum current allowed for clamped input. Shall I search maximum allowed gate current in some general logic family datasheet? I assume after finding this info the minimum resistor value shall be Umax expected/ I max.

My second question is about paralelling 2 outputs of CMOS IC. I think I have seen this in circuits when the IC was connected to power MOSFET in order to achieve faster switching. Are there any precautions before paralleling outputs? Concretelly I would like to drive 17mA signal relay coil with two parallel CD4049B outputs sinking coil via outputs to ground where maximum 12mA per output is recommended for continous operation.

 

[benta]

To your first question:
the 10k resistor is not really needed if your LM339 is powered from the same supply as your CD4013. If they have different supplies that may both be 12 V, then it's needed to prevent the LM339 under power to send 12 V to the CD4013 that might not have power (think also power sequencing).
The 10k is probably selected to limit the current through the CD4013 protection diodes to a safe level.

Second question: paralleling can be done without any problems.

Benta.

 

[Noway2]

To add a note about the paralleling: MOS outputs may be placed in parallel because they have a natural negative feedback effect that causes them to share current. Bipolar outputs, on the other hand do not and one device will attempt to hog all of the current in a runaway fashion. If you use devices with bipolar outputs you will need to put a small resistance in series to provide some negative feedback. Note, in this case, negative feedback means that as the output increases, the driving voltage / current is reduced to compensate, not feedback like in an opamp circuit.

 

[homoly]

OK so basically the current limiter resistor should help when the 2 12V sources should be referred to different grounds with a level shift at least 0.7V activating the clamping diodes and also to limit current when there is voltage on eventually not powered IC ( sequencing during turn ons and turn offs of the device). But I would like to know for the future what is the maximum input current for the gates of CMOS ICs. Is there a difference between different CMOS families or practically the on chip diodes are the same?

Thanks for the paralleling confirmation. It seems it is pretty much the same as in the case of the discreete transistors. Even less painful for the transistors on chip because they are better matched with the switching characteristics. I do remember some application note when for paralleling discreete Mosfets some low pass filter with inductance on gates was recommended to better match the switching controlled with the same signal.

 

[Noway2]

You will have to consult with the data sheet for the particular part for the maximum input current. In the steady state, the input current should be zero or really close to it. The reason being is that MOS architecture has an insulator with a VERY high resistance at the gate. The current, which occurs mostly at switching, is to overcome the gate capacitance which is a parasitic effect. The maximum current will depend on part geometry, but in general, larger parts will have higher currents.

 

[homoly]

This is clear in principle, but as I mentioned before I have checked the

http://www.fairchildsemi.com/ds/CD/CD4013BC.pdf

and only parameter I have found is IIN = 1uA. This seems to me like a steady state maximum current given by a "worst case gate". If I would calculate the limited current for 10k it would give me at 12V-0.7/(10e3+Rdiss)= cca.1.13mA which is far more than Iinmax of 1uA. So If the 10k would have to be effective I would except to found in some datasheet 1mA absolute maximum input current...

For the switching characteristic I have found only the timing characteristic but the transient Cgate charge current should not be an issue ( if I look in situation when one IC output is supplying the second IC input both CMOS ), is that correct?

I was assuming the current limiting resistor is necessary only for the situation where the internal diodes are clamped in the situation the longer transient overvoltage is expected that the one used in ESD protection testing using human body model. So this is why I am a bit confussed now.

 

[zappedagain]

"paralleling discreete Mosfets some low pass filter with inductance on gates"

With two capacitors collected in parallel like this you can get some oscillation as they pass charge back and forth; as thsi varies Vgs slightly you can see it on the drain/source channel. A bit of filtering between the gates reduces this effect. This is typically only an issue in high frequency circuits (transmission line reflections).

I consider this similar to adding a resistor in series with the base on a BJT so you don't get ringing caused by the inductance on the emitter lead.

John D

 

[benta]

Interesting, Fairchild does not want to specify this parameter.
ON Semiconductor does, if you check out the MC14013, maximum input (and output) current is specified as +/- 10 mA.

Benta.

 

[legalimit]

I seem to remember that the LM339 has an open collector output, so the folowing CMOS willned a pull-up resistor on its input.

Hope this helps

 

[IRstuff]

What clamping diode? The clamp diodes on MOS devices are for ESD protection, and have no operational effect during normal operation. A standard CD series MOS device has only reverse-biased clamp diodes, possibly zener, and possibly a field-threshold transistor. Unless the input voltage exceeds either of supply rails, the DC input current should be no more than a few microamps. The ONLY time either MOS or TTL devices get a short circuit current over 100 uA is if the input diodes have been ESD-zapped and are damaged.

There will be a potential transient input current draw if the CLK input is potty, causing the internal feedback path to be transiently connected to the data input.

Fairchild's datasheet DOES specify maximum output current of 8.8 mA at Vout=1.5V.

Likewise, the ON datasheet shows max input current of 1 uA

TTFN

FAQ731-376

 

[homoly]

Thank you for the entries, I have found the app note I was talking about related to discrete Mosfet paralleling:

http://www.microsemi.com/micnotes/APT0402.pdf.

Benta, thanks this current value now makes a sense for me with 10k resistor.

The LM339 is OC indeed, I have connected the pull-up to its output right after placing the comparator.

Now I have finally some idea about current limiting resistor size considerations.

 

[homoly]

OK so the material in the

http://www.ecelab.com/interfacing-opamp-ttl-cmos.htm

is no properly describing the situation as according this information the 10k resistor is not necessary.

Yes I was talking about ESD diodes ( or maybe for some ICs the reverse polarity protection ).

Normal operation is out of question there is no need to do any limiting. My question was related to sizing consideration of series limiting resistor which is recommended when the input of the MOS is connected to edge connector at

http://www.scribd.com/doc/19240355/CMOS-Logic-Data-Book-Dl131D-Onsemi

page 29 and when interfacing the CMOS with comparator ( the ecelab link at the beginning of the entry)

 

[IRstuff]

Page 29 of the app note is specifically talking about ESD protection, and it specifically tells you how to determine the maximum allowable resistance, based on your maximum tolerable propagation delay. As shown in the 2nd figure, the two diodes are reverse-biased during normal operation.

Since the 14000 series CMOS are pretty much slugs as propagation delays go, you can pick higher resistances to provide more ESD protection.

TTFN

FAQ731-376

 

[homoly]

OK the ESD point of view is more or less clear now.

But what is the mening of 10K capacitor between comparator and CMOS. My idea is now the ESD diodes and the resistor creates a lowest possible resistance for a very short duration ESD which current is decreasing in time (as for capacitor discharge ). The eventual transient voltage exceeding VDD+Vd when comparators output going 0V to +Vs or Vss-Vd when going from +Vs to 0V would create practically a short via ESD diodes with a current source represented by comparators output which is not limited compared with ESD capacitor discharge nature and should damage the ESD diodes.

Is this a reason for use this resistor? If yes should it be ommited if the eventual transient voltage on comparator would not exceed levels activating ESD diodes?

 

[IRstuff]

If you read your cited source, you'll see "good practice." The resistor's purpose in life is not just for ESD, since the first example shows no clamp diodes. The series resistors provide two other functions:
> minimization of ringing and other high frequency noises not relevant to the actual signal
> isolation of failed components, so if the driven gate gets fried and shorted out, it does not cause an output failure in the upstream device.

TTFN

FAQ731-376

 

[homoly]

So it seems the 10k value is selected to provide safe enough output current for the most commonly used comparators in the case of permanent short of CMOS input to ground ( I was not sure if this should suppose to prevent the ESD diodes from overloading when they are activated by ringing from the comparator ).

So if I understand it well in this case the priority is limiting and additionally the resistor together with Cgs and PCB track capacitance forms a parasitic but in this case usefull low pass filter.

Thanks again for answer now the resistor sizing is much much more clear for me in different connections.

 

[Noway2]

Homoly,

Let me add to your understanding by providing you with a real world example. I designed a PCB that had a CPLD on it that had a nominal input range of +3.3Vdc with some margin (I forget how much). I made a design fubar where instead of +3.3V, I accidentally applied +7vdc to the input when it was high.

Fortunately, I followed "good design practice" and put a current limiting resistor on the CMOS input to the CPLD. The clamping diode in the CPLD kept the voltage applied to the internal circuitry within limits. The resistor was such that it limited the current through the diode and kept it from being destroyed. The net result was that even though there was a serious flaw in the design, I was able to still use it for prototyping purposes and avoided a costly board re-spin. Without the current limiting diode, the CPLD would have gotten really hot, really fast and quickly failed.

 

[homoly]

Thanks Noway2, so the good news is that the resistor can prevent also the diodes during transient overvoltage or accidental wrong voltage application within some reasonable limits .

So if I get it from information above correctly the resistor sizing consideration for interfacing should be following:

1.) Determine the minimum value according the current carrying capacity of the output of the upstream device connected to CMOS for the worst case direct short of the CMOS to ground.

2.) Theoretically then I should calculate the time constant of limiting resistor and Cgs and PCB track and determine the resistor value which will provide me desired maximum rise time (transfer delay ) but at the same time not exceeding the maximum rise time allowed for the given IC type. Practically maybe instead of calculation it would be better ( for me ) to increase repetitively the value of resistor and measure the dynamic parameters.

The with theoretical or practical approach get as high limiting resistor value as possible fulfilling the required dynamic parameter.

For the ESD immunity increasing via introducing serial resistor in connector leading out of board I will rather consult some book because I have a feeling it is not so easy...