homoly
Electrical
- Jun 11, 2007
- 100
Hello,
I have been involved in modifications on the existing device using CMOS ICs with which I do not have practical experience and for this reason I would like to ask few questions.
In new circuit I would have to connect the output of LM339 with CD4013B flip flop. I have found article recommending series resistor between comparator and CMOS: .My case is Fig.1 with 12V supply. My question is about the resistor sizing why exactly the 10K value is selected? After some research I have found the upper limit of resistor value is given by a time constant of Rlim and gate&PCB tracks capacitance , that in the case of 15 VDD supply CMOS the rise time of the input signal should not exceed 4-5us to avoid output oscillations.
I assume the lower value is given by the maximum allowed input current to the gate when internal clamping diodes are activated by ESD or transient overvoltage. Here I found in datasheet only the IIN = 1uA which seems to me as the maximum current in normal operation defining input resistance quality not the maximum current allowed for clamped input. Shall I search maximum allowed gate current in some general logic family datasheet? I assume after finding this info the minimum resistor value shall be Umax expected/ I max.
My second question is about paralelling 2 outputs of CMOS IC. I think I have seen this in circuits when the IC was connected to power MOSFET in order to achieve faster switching. Are there any precautions before paralleling outputs? Concretelly I would like to drive 17mA signal relay coil with two parallel CD4049B outputs sinking coil via outputs to ground where maximum 12mA per output is recommended for continous operation.
I have been involved in modifications on the existing device using CMOS ICs with which I do not have practical experience and for this reason I would like to ask few questions.
In new circuit I would have to connect the output of LM339 with CD4013B flip flop. I have found article recommending series resistor between comparator and CMOS: .My case is Fig.1 with 12V supply. My question is about the resistor sizing why exactly the 10K value is selected? After some research I have found the upper limit of resistor value is given by a time constant of Rlim and gate&PCB tracks capacitance , that in the case of 15 VDD supply CMOS the rise time of the input signal should not exceed 4-5us to avoid output oscillations.
I assume the lower value is given by the maximum allowed input current to the gate when internal clamping diodes are activated by ESD or transient overvoltage. Here I found in datasheet only the IIN = 1uA which seems to me as the maximum current in normal operation defining input resistance quality not the maximum current allowed for clamped input. Shall I search maximum allowed gate current in some general logic family datasheet? I assume after finding this info the minimum resistor value shall be Umax expected/ I max.
My second question is about paralelling 2 outputs of CMOS IC. I think I have seen this in circuits when the IC was connected to power MOSFET in order to achieve faster switching. Are there any precautions before paralleling outputs? Concretelly I would like to drive 17mA signal relay coil with two parallel CD4049B outputs sinking coil via outputs to ground where maximum 12mA per output is recommended for continous operation.