CPLD + SRAM == Cheap FIFO (albiet... slow)

[Yashu]

Does anybody have a link to VHDL code to transform say... XC9572 &
CY7C1399 into a 'slow' Dual 16Kx8 FIFO (for about $3.65 in Qty 100)

IDT's stuff is too $$$$ and I don't really need the 'instantaneous'
simultaneous access from "both sides"... handshaking with ready/done deal
is good enough.

 

[cbarn24050]

Its probably easier to use a small micro and a ram chip.

 

[Yashu]

I don't want it THAT slow.. plus, I'd like 8-bit latched parallel intfc's from both sides so the uC's on each end can just latch the data they want to write... say go.. and come back about 2us later with the next byte to write.. since the composite FIFO will be done storing the last byte.

 

[itsmoked]

How about just using a micro and its internal ram as a state machine? You could hit 2uS pretty easily I think.

 

[cbarn24050]

Not too many micros with 16k internal ram. If he cut it down to say 8k it would be doable.

 

[Yashu]

Repeat: Does anybody have a link to VHDL code to transform say... XC9572 &
CY7C1399 into a 'slow' Dual 16Kx8 FIFO

 

[cbarn24050]

Ive just seen the new PIC24H micro, 16k ram and dma, so that would seem to meet your spec, apart from the price but thats allways going to be impossible. To do it with a CPLD you need 10 pins/logic block for each external interface, 24 for the ram,28 for the 2 14 bit counters plus an undefined amount extra to tie them together so you need at least an XC95108.