Creating a Power-on reset pulse in a CPLD

[felixc]

Hi,
I am required to create a power-on reset pulse to trigger external registers ASAP after power-on so that valves will not open spuriously. The system reset pulse comes after one second, too late. Of course the systems are in the field now... There are no inputs that provide a delayed signal that I could use to generate a known condition to a state machine. There is no way to tell the registers in the CPLD (a xilinx XC9500 series) to power-on at a given state, from the compiler. How can I make the state machine to start at the right state at power-on.
Thanks
Felixc

 

[itsmoked]

AH I think you're pretty much screwed.. This is a common amateur mistake. Everyone makes it.. once. A system must be designed from scratch to not allow active wrong-state outputs during boot up.

Often logic devices are high impedance inputs before being initialized. In this case pull downs etc., should be employed to prevent these spurious excursions. Can you solve this by adding pull downs now? Can you put a RC into the effected output channel? Like a small resistor and a big cap to force the output into taking a while to switch? This may cause operational problems though. You need to check the viability of this string-and-paper solution.

Can you reprogram the CPLD? If you can maybe you can run all the affected outputs thru a gate that only switches once the CPLD gets talked to by the fully rest running system. Identify a signal that starts after reset and use it to "un-inhibit" the problem signals.

Keith Cress
Flamin Systems, Inc.-

http://www.flaminsystems.com

 

[VEBill]

Would this work?...

Divide the entire system into two parts: the control system (CPLD, etc.) and the controlled system (valves, etc.). Split the power supply so that the former controls the power supply to the latter.

Have the control system power up first (exactly as it is now), regain its mental health (reset), and then have it (the control system) apply power to the other half of the system (the parts that move) probably using a relay and/or contactor(s).

All you have to do is make darn sure that you design the control of the new relay so that at least it is always under control. I'd probably design it so that it needs two outputs, both intentially set opposite of default, before it would move to the ON position.

There will be a slight delay during turn-on, but assuming that the entire system is being turned on by a human, then he can leave for work a couple of seconds earlier in the morning to compensate.

In summary, let the control system apply power to the valves at the very end of its own boot-up sequence.

This is a sort of 'Macro' solution except for the detail that you need to modify the control system to control the new relay.

 

[felixc]

During development my customer has accepted the one-second glitch, but their production people don't like it as different systems may not "sound" the same when they power-up.

Instead of lasting one second, the system reset is only a short pulse that happens after one second. Lots of registers in the CPLD are initialized with this short pulse. My bug is before the pulse. You saw the right thing itsmoked and this is what I tried first, but the problem is that I have no signal of a known value that I can use to gate the strobes before the reset pulse comes in. Whatever I try steers me back to this initial condition.

I can reprogram the CPLD easily. I'm trying to find a programming trick that can let me avoid a rev change on my pc board. Plus a mod on the existing boards. So far it looks like I will have no choice but to connect a RC to an unused CPLD pin and use it to make an additional POR signal in the equations.

 

[chai18]

How much logic is available in your CPLD?

 

[sreid]

chai18 may be going here.

Create,say, an 8 bit binary counter that free runs on power up. Then decode all states except one equals reset. When that count is reached, release reset and freeze the counter. This does not guarantee a reset at power up but it does 255 out of 256 times.

 

[Noway2]

Also make sure you did through the synthesis and general options available on the compiler. Some devices have a global power on reset that is generated internally in addition to accepting a global reset pin.