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CT Saturation - asymmetrical faults 1

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bspace123

Electrical
Sep 3, 2009
27
Hello

We have completed a fault study to identify symmetrical fault levels of 50kA RMS and asymmetrical peak fault levels of 100kA according to IEC60909 using SKM.

CT's proposed by the supplier are 2000A/1A 10P40. This implies CT's will not saturate for the RMS symmetrical fault current (i.e. 10% accuracy up to 80kA).

We want to ensure CT's spec'd do not saturate during the asymmetrical fault. How do we ensure this will not happen as the asymmetrical fault level will be accompanied by a DC offset (ie. RMS will be higher)?
 
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Here is something to size CTs so that you don't have any CT saturation. You'll like end up with really big CTs.


Here is a spreadsheet to show the impact of saturation on the fundamental component.

It often will be impractical to size CTs to eliminate saturation completely. Modern relays filter out the fundamental component and you have to have a decent amount to saturation often for you to care.

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If you can't explain it to a six year old, you don't understand it yourself.
 
my understanding is that RMS asymmetrical is typically 1.6x RMS symmetrical. Hence, RMS asymmetrical fault current in this situation is 1.6x50kA = 80kA, so if CTs are sized to 10P40 @ 2000/1 (i.e. 10% accuracy upto 80kA), then these should do the trick?
 
The concern is DC saturation. Depending how slowly it decays, you might need a lot of core iron to avoid saturation.

Here are some more links I have on CT saturation.





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If you can't explain it to a six year old, you don't understand it yourself.
 
I use DC transformers for that. They are designed to handle the DC component.

Rogowski coils with an integrator that can handle the maximum (peak + DC) current are also a good choice. The air in the Rogowski coil never saturates. And an integrator that can handle a 1-to-10 000 ratio can easily be built with today's low drift opamps.

Gunnar Englund
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Half full - Half empty? I don't mind. It's what in it that counts.
 
As mentioned, it's the dc component that is the killer, not so much the higher ac current. There is no asymmetrical current without dc offset. The key is making sure you have calculated an accurate X/R ratio at the fault point. Also, at very high current levels, often relays are tripping on instantaneous element, and this may still happen even if CT is on its way to saturation.
 
A key point to remember is that there is also a burden specified as part of the CT's accuracy rating...for example 10P40 - 30VA. That means that the CT error will be less than 10% up to 40 x Inom when loaded with 30VA. The burden and the over-current factor are related proportionately. Therefore, if the connected burden in this example is really 15VA, then the CT accuracy will be <10% up 80 x Inom.

Also, 10P40 doesn't mean that the CT won't saturate up to 40 x Inom, but rather that the error will be less than 10% at 40 x Inom (at rated burden). For a 1A rated secondary...40 x 1A = 40A secondary and 10% of 40A is 4A, so it means that the excitation current cannot exceed 4A @ 1200Vsec (30VA @ 1A = 30ohms, 30ohms x 40A = 1200V). 4A excitation current is likely well past the knee-point region and considered to be in saturation.

 
To add further to scottf, no mention is made as to the application as well. Unit protection? High impedance? Instantaneous protection? Time delayed? CT saturation will depend on the actual connected burden as well as the degree of offset which in turn is dependent on the X/R. For many applications a transient factor of (1 + X/R) is used. This is worst case and will assure that CT saturation will not take place during the transient period of the fault current waveform (i.e. during the lifetime of the DC offset).

But since this appears to be a Class P (or PX) CT it does not seem to be for a differential scheme? Would be good if the OP could provide some further application details.
 
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