DAC7571 latch up

[logbook]

I am running a DAC7571 12 bit I2C DAC from a 5V rail butteh load is going to a -5V power rail, the Thevenin equivalent circuit being a 1240R resistor to -3.8V. At power up the DAC latches at -2V and will not recover. This circuit and this load worked fine on the last two issues of pcb and now it doesn't work anymore :-(

I tried a standard diode from the DAC output to 0V to prevent the output going too far below its power rail but that didn't stop it latching.

Suspiciously the data sheet of the part was just updated in August 2005 but I haven't yet spotted the changes.

I thought CMOS latch-up was a thing of the past. I'm off now to try to find a schottky diode in a last desperate bid to fix this fault. Any other thoughts?

 

[IRstuff]

CMOS latchup is inherent in the structure of the devices. Most technology and topology measures simply make the device more robust. However, variations in power sequencing, signals at off voltages would still be able to start a latchup.

Additionally, it's also possible that the supplier went through a mask or process change that would aggravate latchup.

TTFN

 

[melone]

What changed on this issue of the PCB? Perhaps that would be a good place to start.

 

[logbook]

Melone,

nothing electical changed on the output of the DAC, although the whole layout has changed. Frankly this stuff is all working at "DC" so layout issues shouldn't be relevant. the fact that winding the negative power supply down to zero and back up is a clear indication that the output buffer on the DAC is playing silly beggars. Since the DAC is driving a 1µF load (via 500 ohms), load track capacitance (must be less than 10pF) is not an issue.

I bet they have done a mask change to a smaller CMOS geometry making the latch-up current threshold lower.

 

[itsmoked]

I agree with IRstuff the biggest likelyhood is power supply sequencing.. Could also have a geometry change as you suggest tossed in too. Try starting up your system's positive rail then allow the negative rail to come on. See if you can get away with that. If so then you could also have gotten a larger regulator cap (in the tolerance realm) that make the positive rail come up slower or a smaller cap in the negative that makes it come up quicker. (or both)

If this ploy works you can try changing cap values or delay the negative rail by adding a small amount or series resistance etc.

 

[logbook]

I'm testing the board in isolation running off a bench 3 output power supply. It's possible that if I run it from the ± variable pair rather than from the semi-fixed positive and large varibale negative that it will be more balanced in the start-up phase.

In the full system the power supply is massively over-rated for power and would probably not be concerned by even large power supply capacitors.

I am now thinking about a FET on the DAC output to the positive rail. I am just wondering if there is some simple configuration that holds the output to the positive power rail until the positive power rail reaches 3V. An SOT23 FET and a wire link per channel would be an acceptable bodge, if it worked.

 

[itsmoked]

There are a lot of supply staging controllers now. A hole lot! Owing to PC mutherboards all requiring them now. Check them out. Not necessarily to use but to learn how they tend to do it.

 

[melone]

Have you thrown a scope on the supplies to verify the power up sequencing is what you think it is? Triple check the data sheet for sequencing requirements. I just ran into a problem where a device needed to have the I/O rail come up BEFORE the core rail. Perhaps, the design has been violating the device specs the entire time, and know you are getting parts that are "less robust".

 

[logbook]

Melone,
the power supply sequencing is a bit boring at the moment in the sense that it is a bench power supply I am using to test the boards. The DAC7571 data sheet won't mention "power supply sequencing" because it is a single rail device! I doubt that it will discuss pulling current out of the output buffer before power is applied to the part, but I do have to wade through this revised data sheet to see what has changed anyway.

I seem to recall modern CMOS logic devices requiring 10mA substrate current before the output stage latched, but this linear CMOS analogue output buffer evidently requires less than this amount to latch up.

 

[logbook]

I fixed the latch-up using a schottky diode to the 0V rail.

 

[itsmoked]

Thanks for the follow up. Glad u solved it.