Delaying bus differential 1

[Mbrooke]

Two quick questions:

1. In a high impedance differential protection system, is there any way to know or calculate the stress an 8 cycle delay can cause on the MOVs and resistor during an in-zone fault?

2. Are there any low impedance differential relays (ie sel487, B90) where a differential trip can be delayed?

 

[davidbeach]

For the high-impedance it's just an energy calculation, but given the design of using a lockout relay to get the resistor and MOVs out of the circuit as fast as possible I'd be surprised that you can get the necessary energy levels.

For the SEL-487B the differential doesn't cause a trip unless it's in the trip equation. Instead of putting the differential elements in the trip equation just use them as inputs to timers and put the output of the timers in the trip equation.

What you'll lose if you do that is the high-speed determinations made before CTs can saturate. If you don't have CT saturation problems that won't be an issue.

 

[Mbrooke]

With the 487B, I can easily configure these timers not to initiate tripping if the differential stops picking up say after 5 cycles? Basically I don't want a "seal in" phenomenon.

 

[Mbrooke]

Also, scratch the high impedance idea. Came across this in the manual:

Always connect external shorting contacts from the lock-out relay to limit
fault voltages applied at the relay input terminals to 4.0 cycles or fewer. For
example, wire an output contact from the SEL-587Z to operate an 86 lock-out
relay, which in turn shorts the inputs to the high-impedance elements. Do not
rely on the circuit breaker to clear the fault current, because the circuit breaker
operating time may exceed 4.0 cycles or may fail to open altogether.

No such limitation exists for the 487B, correct?

 

[davidbeach]

The current inputs to the 487B are rated 15A continuous, 500A for one second, and 1250A for one cycle. Hopefully you'd be well below 100A and well below 1 second, so the relay shouldn't care.

As long as the dropout time of the timer is set to zero, the timer stops timing as soon as the input condition is no longer present. With a PU time of 8 cycles, the condition could be there for 7.75 cycles, out for 0.25 cycles, back in for 7.75, etc. and never trip. Throw in a 0.5 cycle DO time and you'd get your trip. Both PU and DO are independent and could either be zero.

 

[Mbrooke]

Very good, certainly doable.

 

[JJHorak]

Reliance on lockout relays to prevent damage to high impedance bus diff relay from damage has been an industry standard since the invention of the high impedance bus relay (1930's?) and I am unaware of a concern about their failure and subsequent damage to the relay. Or maybe I am just unaware? I vaguely feel the industry is moving to low impedance bus relays for other reasons than the relay damage concern. Problems with high impedance relays are they are single function relays, no other relays can be put on the same CT string, they effectively require all CTs to be the same ratio, and they do not have good event reports. And engineers looking for billable hours like the additional difficulties of setting up low impedance relays, of course.

J. Horak, P-R Engineering, Colorado

 

[Mbrooke]

I think one push for low impedance has been from "electronic lockout" where the relays themselves perform the lockout function.


In my case I am debating increasing the bus differential trip by several cycles, and if I do, an SEL587Z would be exposed to many more cycles of differential voltage before the lockout relay shorts the CTs. Even without a time delay, High impedance relays need have their CTs shorted because a failed circuit breaker might take 12 or more cycles before the bus becomes de-enrgized. That whole time the relay is being fed elevated voltage.