Desired crystal capactitance/resistance? 2

[MacGyverS2000]

All of these years I've designed uP circuits with a blind eye towards the crystal portion. I've always felt guilty about it, so I decided to remedy the situation starting with my current project, which uses a PIC and a 20 MHz crystal.

Now that I've read the datasheets for the crystal (an Epson MA-505) as well as datasheets and design guides for crystals, I think I was happier when I was designing blind

My first question is this...what value of caps should I be designing in for proper oscillation?

More capacitance means a more reliable oscillation, but also means slower startup times. The suggested range from Microchip is 15-33 pF for a 20 MHz chip, so I chose 18 pF based upon the load capacitance listed by Epson for the chosen crystal...although I'm not sure if that's the correct way to do it (the datasheet for the PIC suggest testing was done with a similarly spec'd crystal, also from Epson, but doesn't specify anything other than the range given above).

I'm unsure as to where I can find drive power on the datasheet, or if I'm supposed to calculate it based upon the external cap values and crystal frequency.

My second question...do I need a series resistor?

The PIC datasheet says it's needed if the crystal is AT cut (which I don't believe it is), but Epson's design notes goes into some pretty heavy testing to determine the value.

Please, someone help me out with some useful rules of thumb on this one to get me back in the game without a minimum of headache.

Thanks!

 

[Warpspeed]

Ah yes interesting questions indeed.

The first point is that the crystal manufacturer has no clue as to what circuit his crystal is going to be used in. So he just provides a parallel resonant crystal at the marked frequency when the specified capacitance is connected across the crystal.

The microcontroller manufacturer also does not know if you are going to use a crystal, a ceramic resonator, or an external digital clock source. If you are going to use his CMOS input buffer as a linear biased amplifier, it will need a dc feedback resistor from the inverted output. This resistor must be large enough to not load the ac signal, but it must be there to provide dc bias. Probably something between 100k and 10 meg will work fine without really having to worry about the actual value too much with CMOS impedances.

With these sort of (collpits oscillator)circuits, the crystal must have an ac centre tap so the input and output sides of the crystal are at the optimum 180 degrees phase difference for maximum positive feedback. The simplest way is to connect two capacitors in series across the crystal and ground the centre.

If the crystal manufacturer says his crystal needs 30pf, a pair of 60pf capacitors would do. BUT the circuit tracks and the ic have stray capacitance associated with them. So to get the required 30pf much smaller physical capacitors need to be added. Most designers seem to use 15pf to 22pf, and it is probably as good a guess as anything.

Strictly speaking the crystal should oscillate only at its proper marked frequency with the correct total capacitance. In practice the actual capacitance is not going to make a large difference to frequency.

The series resistor is probably a good idea. The CMOS output switches hard from rail to rail at a few hundred ohms impedance with a square wave. The crystal is a high impedance resonant ac circuit, and is not going to be too happy having one side shunted with a relatively low drive impedance. The CMOS output is not too happy either driving a capacitive load, even if it is only maybe 60pf.

The solution is to fit a series resistor of usually about 4k7 between the CMOS output and the crystal. It will oscillate fine without it though. If you make the resistor too large, the extra RC phase lag and reduced amplitude, are going to reduce the positive oscillator feedback.

Design engineers have sleepless nights about stuff like this. It is easy to get your own microcontroller going on the kitchen table, but it is quite another thing to design a new product that will be manufactured in the hundreds of thousands, and every one must oscillate reliably over a wide temperature range, with crystals from several different suppliers.

Your best bet is to just copy established design practice and not worry too much about it.

 

[Skogsgurra]

This simply has to be the best thread this year!

Like MacGyver, I have told myself that I shall dig into these questions - but not just now, later, perhaps. And that later never happened. I am glad that someone took it a step further.

I am more than glad to read Warpspeed's answer. It clarifies a lot of things - like the Colpitts oscillator structure and the capacitive center tap. I didn't even know about that, but it is obvious now. The best part is that "don't worry, be happy" conclusion.

Stars for both of you!

 

[MacGyverS2000]

Warp,

If I understand you correctly, the 18pF value I read off of the crystal's datasheet says the crystal will oscillate at 20 MHz when presented with an 18pF load, correct? So, the idea is to design the loading caps and stray trace capacitance to equal 18pF.

For reference, here's a link to the design guide from Epson's website...

http://www.eea.epson.com/go/Prod_Ad...rystals/go/Resources/TECHNOTES/OSCDESIGNGUIDE

...and the typical PIC circuit seems to follow Figure 2.1, an unbuffered gate with integral Rf.

If the two capacitors are labeled Cg and Cd, then finding the load capacitance, Cl, in pF is...
Cl = [(Cg * Cd)/(Cg + Cd)] + Cs
...where Cs is the stray trace capacitance (a couple of pF for dual-layer boards). As Cl drops below this optimal value, the crystal frequency will increase, and vice versa.

With the above in mind, my thought of using 18pF caps for a crystal which requires Cl=18pF is a bit too low. I should, therefore, probably increase the caps to around 30pF (I believe 27pF and 33pF are common values). My traces are about 1" long, so I'll probably go with the 27pF cap.

The crystal datasheet lists a max Rs of 50 ohms, so I don't believe I need to add anything else in. Max drive level is listed at 2mW. The tested crystal listed in the PIC datasheet was an Epson CA-301, which also has a max drive level of 2mW (with a recommended level of 10-100uW), so I guess I'm OK, but I would still like to know an easy way to determine the actual drive level (the Design Guide listed above gives a testing method, but it involves miniature current sense coils and such).

 

[Warpspeed]

It sounds like you have already reached a satisfactory design compromise.

The subject of drive level opens up a whole different can of worms. The crystal is physically vibrating at its exact mechanical resonant frequency, and has a lot of stored internal energy.

Like the opera singer shattering the wine glass, at some point you can fracture a crystal if you drive it hard enough. The problem is one of extremely high internal Q.

But how much external energy you feed in, is not really a measure of what can destroy the crystal, but it is really the only thing you can measure. 2mW is not much, but I suppose if the internal Q was 800, there could be 1.6 watts of built up oscillating mechanical stresses in there, something to really think about.

Another thing that has always fascinated me about oscillators is how they start up. A good oscillator will have a particular frequency where the gain is (much) more than one, and the phase around the circuit is 360 degrees. But the only thing that can ever start it off is circuit noise.

A little bit of broadband noise goes around the loop and comes out a little bit bigger at one particular frequency, and hopefully attenuated at all other frequencies. It keeps going around and around getting bigger and bigger until something eventually limits the rise in amplitude. Fascinating stuff.

 

[Madcow]

I usually follow these guides

http://ww1.microchip.com/downloads/en/AppNotes/00588b.pdf

http://ww1.microchip.com/downloads/en/AppNotes/fact001.pdf

and test in a chamber cold at high and low bias,cycling power. Then hot at high and low bias cycling power.

Best of luck

 

[MacGyverS2000]

Bringing this back to the top, as well as adding some more (hopefully) useful info. Yet again, I was recently stuck working on a crystal-based problem that I've often overlooked...drive power.

In the past, I blindly assumed the correct drive power being provided by the chip, never questioning that it may be too much and overdriving the crystal. A bit of forethought and a small sampling of mathematics later, we're able to determine the correct value for Rs, the series resistance in the feedback loop ocassionally required to reduce drive power levels.

First off, we need a few pieces of data before we can calculate Rs. We need the crystal's max drive level (in Watts), the Effective Series Resistance (ESR, in ohms), and the voltage swing of the driving element. The steps are as follows:

1) The current through the crystal (and Rs) is calculated as Ix = ((Px/Rx)^0.5), where Px is the crystal's max drive level and Rx is the crystal's ESR.

2) The voltage drop across the crystal is calculated as Ux = ((Px*Rx)^0.5), using the same values as above (result in Vrms).

3) The voltage drop across Rs is calculated as Ur = Ud - Ux, where Ud is the driver's output voltage in Vrms.

4) Finally, Rs can be calculated as Rs = Ur/Ix.



This all came up as I transitioned from one crystal type (with a max drive level of 2 mW) to another (max drive level of 50 uW). I do not yet know if the PIC chips will overdrive this significantly more sensitive crystal without the use of Rs (I hope so), but wanted to bone up on the material, just in case.

The new crystal has Pmax = 50 uW and ESR = 50 ohms. From this, I get an Ix = 1.0 mA and Ux = 0.05 Vrms. I cannot figure Ur or Rs yet, as I do not know the voltage swing of the PIC drivers (the datasheets are either too sketchy or I'm missing the obvious).

Hoping someone else finds this material useful...

 

[MacGyverS2000]

LOL, I reread my earlier post and came across a comment on the crystal Microchip used in their own tests (datasheet creation):

"The tested crystal listed in the PIC datasheet was an Epson CA-301, which also has a max drive level of 2mW (with a recommended level of 10-100uW), so I guess I'm OK, but I would still like to know an easy way to determine the actual drive level"

If Epson recommends a drive level of 10-100uW, I'm reasonably comfortable in assuming Microchip provides a drive power somewhere within that range (the circuit includes no Rs). If my new crystal has a max power of 50uW, I would say an Rs is more than likely in order.

I'm still left with the final question of what value of Rs to use, but I have a feeling it may eventually be determined by trial and error. Pop a 20 ohm resistor in the circuit, scope the waveform on the crystal (which will mean temporarily dropping one of the caps by 10 pF to use a scope probe with 10 pF capcitance), and recalculate from there. It's not pretty, but it should work.