Differential pair length matching for GigE/100M Ethernet

[zappedagain]

There's a fairly common guideline for GigE/100M Ethernet PCB routing on the web (that I won't mention here, yet) that states to "keep the differential pair trace lengths matched to 5 mils (0.005 in, 0.127 mm)". Does anyone know the basis for that? It seems like a really nice design goal ("if you can hit that you'll have no problems"), but how much effort is it worth? It seems like overkill.

My thoughts:

125 MHz is the GigE carrier (on 4 pairs), so to keep the eye open I need to pass the 7th or eight harmonic (1 GHz).

FR4 has a propagation rate of 170 pS/in so 1 GHz has a wavelength on board of 5.88 inches. If I want my auto-transformer cancellation better than -40 dB (1%) then I need a length match better than 0.058 inches. Did they throw another 10x on that to minimize the error effect (-60 dB)?

It all seems a bit moot as the CM rejection on most GigE transformers drops from -50 dB at 1 MHz to 15 dB at 200 MHz so that extrapolates to negligible CM rejection (0 dB) around 1 GHz. The auto-transformer turns matching is only specified to +-2%, so worst case is only -34 dB. My EMI testing experience tells me you really aren't going to get much more attenuation than that with a single component.

So matching to 50 mils (1.25 mm) will not degrade the auto-transformer operation by more than -40 dB at 1 GHz (and 50 mils also happens to match another guideline on the web published by Intel). That seems more real-world.

Did I miss something?

Thanks,

Z

 

[VEBill]

When people install 8P8C (RJ45) connectors onto Gb Ethernet cables, I doubt that the wires in that case are length matched to anything close to that level of precision (0.005").

Such external cables may ultimately connect to the very same magnetics, so this comparison might be a useful sanity check.

 

[MacGyverS2000]

You're going to introduce several mils of error just in etching of the board, how your layout package calculates line length (Altium, for example, only recently switched to a somewhat more accurate center-of-trace method that pays attention to connection angles between traces/pads), mis-match at the copper-to-component leg interface, etc.

The idea is, however, to match every item in the path as closely as possible so that items that are not matched closely do not have as nasty of a cumulative effect. Wire side of the magnetics is a different ballgame.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[zappedagain]

VE1BLL - I don't think its practical to open the spec up as loose as the cable spec. Assuming the cable picks up the common mode noise anywhere along the length, it can effectively look like a well matched pair at the connector. From there the filtering is all up to the PCB and components.

Mac - the open question is how important is this? When the pair turns a corner I'll get a length mismatch due to the different radii. I can make that up elsewhere with accordion traces, but then I disturb the differential impedance by twiddling the width between the pairs. References I've found so prioritize length matching over impedance matching.

I'll keep digging into this and see what I find. Thanks.

Z

 

[MacGyverS2000]

Length should be prioritized over impedance... poor length matching will result in an incorrect symbol being recognized. Considering the tight timing requirements at Gig speeds, the signal from one side of the diff pair does not have to be delayed by much compared to the other side for an incorrect/missed symbol to happen.

Ideally, you design your single trace impedance to be as near 50-ohm as possible, so even as the differential pair as a whole slides away from 100-ohm due to trace separation, each line individually will remain close to 50-ohm. There is a bit of iteration in terms of the stackup involved here. Given the back and forth required, I'm pretty happy if I get a single-ended impedance of low-50's while also achieving a diff impedance of near 100-ohm as possible. Last design, I believe was slightly under 54-ohm SE and 101-ohm DIFF. You will never get perfect 50-ohm SE and 100-ohm DIFF, but your SE is going to float upwards more than the DIFF will.

Generally the best method is to rotate chips 45° at a time until the number of CW/CCW turns the pair makes are equal. If you can't equalize the number of turns, the inner/shorter trace will need the serpentine. Place the serpentine as close to the mis-match location as feasible so the transmitted differential signals remain matched in length for as long into the trace(s) as possible. For bi-directional lines, this is not always possible.

If you hit via pairs (like for 50-ohm resistors to ground) near turns, treat each side of the vias as separate entities in terms of length. In that case, the inner/shorter trace on either side of the vias will need a serpentine.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[MacGyverS2000]

On a related note...

When RF lines are transitioning from 50-ohm impedance to component pads, its typical to put in a "cone", widening the 60-ohm line to the pad size to reduce the impedance mismatch. I carry that design trait over to my diff pairs.

Most examples will show the pair separating as they approach a component, then enter the center of the component pad's face. I prefer to keep the traces together as long as possible and enter the component pads at their corner, leading to a natural "cone". That can be difficult in some packages, such as Altium. As I near the pads, Altium autoroutes exactly as the examples show... I will go back and remove the last few turns so that I can manually route each side of the pair as I suggested. It's a bit more manual work, but it makes me all warm and fuzzy inside knowing I routed the trace as best as possible.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[zappedagain]

I'm starting to understand the math behind this now:

IBM produced a paper about this sometime before 2010:

http://www.ieca-inc.com/images/EMC_CommonMode.pdf

Applying this model to GigE with a 125 MHz waveform shows that a 5 ps delay will introduce a -60 dBuV common mode voltage (from a 2 Vpp sine or a +-1V square wave with 0.8 ns rise/fall times) onto the cable. 5 ps is 29 mil on FR-4, so 5 mil gives about 15 dB of margin.

Z

 

[MacGyverS2000]

I assume you're also paying attention to material weave type/size?

Dan - Owner

http://www.Hi-TecDesigns.com

 

[zappedagain]

I've only known weave to be an issue at 25+ GHz. I agree, the right material for your frequency range is key.

I pulled up the drawings for an older design that has 1000s of units running in the field for 5-7 years with no issues. The GiGE port has a worst case mismatch of over 255 mil in a differential pair and over 660 mil of pair to pair mismatch, and still passed CE Mark emissions with 18 dB of margin. One caveat is that design does have some odd shielded Cat5e cables inside the enclosure (3" of cable with 1" of shield in the middle with 1" pigtails on each end). I'm not sure if that was a fix for an EMC issue or a fix for other signal integrity issues.

I believe the pair to pair mismatch is insignificant compared to the cable pair to pair mismatch; GigE is specified to work with up to 50 ns of propagation delay variation between the pairs, so 170 ps from a 1 inch routing mismatch is trivial.

My takeaway is that with perfect matching you can pass EMI/EMC testing with a lot of other things going wrong. Even with 51 times the 'golden' 5 mil length mismatch this circuit still passed. Everything else in the system (impedance, shielding, grounding, etc.) may have been just right.

Z