Discrete FET driver turns off slowly. 1

[schnell]

Hi,

I have come up with two cheap FET gate driver circuits for driving the gate of a power mosfet in a switch mode solenoid driver.

The PWM signal is provided by the output pin of a microcontroller.
The solenoid current is 200mA.
The FET Vgs(th) should be between 0.8V and 3.5V


****************
Complimentary pair gate driver schematic:-

http://i56.tinypic.com/2zh136o.jpg

...the above "Complimentary pair gate driver schematic" gives a slow turn off of the FET since there is a lingering Vce(sat) voltage of the PNP BJT.

...here is the FET gate voltage showing the slowly declining FET gate voltage at turn off..........................

FET gate voltage with complimentary pair drive:-

http://i52.tinypic.com/xn5h8z.jpg

.....in order to make the FET turn off quicker, the following adjustments were made.................


*******************
Adjusted Complimentary pair gate driver:-

http://i55.tinypic.com/v7t5sj.jpg

having the diode D2 in the Adjusted Complimentary pair gate driver gives a faster turn off of the FET.

..................the diode D2 in the "Adjusted Complimentary pair gate driver" also ensures that there is no shoot-through current by 'slamming' off the PNP BJT when the NPN conducts.

I assume that since the driver devices are BJT's, they will offer more resilience to transients coupled through the Drain-Gate capacitance than circuits which directly drive the FET from the microcontroller port.?

(its my belief that its FET gates that are the most susceptible thing to damage by transients and ESD....BJT's are more robust?)


Does any reader know of a technique of adjusting the above schematics so as to make the FET gate voltage go to zero quicker when turn-off occurs?

 

[IRstuff]

Unless you're prone to touching the FETs with ungrounded fingers, ESD is not an issue for a device buried on a board.

However bad your original circuit, it seems to me that you made it worse with your "adjustment."

In your original configuration, the two BJTs are configured as a linear buffer mode, which seems to be not what you desire, since you're basically running it as a logic gate, i.e., ON or OFF. Running the PNP as you have in the second circuit is a non-starter, since you have nothing to source base current except the residual charge on the FET gate. This is the same problem that you had on the original gate, but instead of being driven directly by the controller, the PNP is worse off because it's being pulled down by the 1K instead of the controller driver output impedance.

Two possible choices might be:
> Change the original circuit's pulldown to an NPN and configure the circuit like a TTL totem-pole output. This would require and inverted signal from the controller to drive the pulldown. You can phase the drive signals to ensure break-before-make operation.

> Reverse the two BJTs in the original circuit so that they are both running as common emitter vs. the emitter follower that you had before. The downside will by that the transition times would have both BJTs on at the same time. Your drive signal would need to be inverted.

TTFN

FAQ731-376
Chinese prisoner wins Nobel Peace Prize

 

[schnell]

the thing is, with TTL totem pole, there is more shoot-through current, as you suggested....also, its three BJT's instead of two.

If you mean "phasing" the switching of the two TTL totem pole transistors with two microcontroller pins....then that is out of favour for us, because we don't have two uC pins available for each driver.

the circuit i submitted above is not that bad, but its just that it'd be nice to get the PNP to more quickly discharge the FET gate down to zero volts.


Incidentally, the PNP part of my circuit is based on page 14, figure 13, of the following.......

http://focus.ti.com/lit/ml/slup169/slup169.pdf

...the complimentary pair idea is based on page 12 , figure 10, of the same article.

 

[IRstuff]

The PNP approach is ostensibly fast in the initial portion of the turn off, since it's got its highest gain with a large Vce and plenty of base current. Note that the PNP pulldown is not necessarily a problem if your FET has a high threshold. There should only be a problem if your FET's threshold is relatively low, compared to the Vbe of the PNP. Your FDS4559 has a min threshold of only a volt.

So, another option is to switch out the FET for one with a higher threshold, which would allow the FET to be turned off before the PNP goes into its turn-off tail. Or, an ugly option is to put a Shottly power diode in the source leg of the FET, to effectively increase its threshold, relative to the driver.

TTFN

FAQ731-376
Chinese prisoner wins Nobel Peace Prize