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Doubt on copper pour area width for current capacity 1

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gmarocco

Electrical
Jan 24, 2017
1
Hy, I am designing a power distribution board using the OR-ring topology The board has to carry about 34A per contact
( and 140A in the common nets. I am designing the board using 4 layers. In order to route the power nets I have used a copper pour area equal for all the 4 layers. I plan to use 70um copper for both external and internal layers.
I have checked Saturn PCB design but I am not sure regarding the option "Plane present".
Has this option to be checked when the signal is routed using a copper pour area or when the signal is routed
using a track sorrounded by a ground plane? For example using a 70um thickness for both internal and external layers (with 20°C of temperature rise) I obtain with the option "Plane Present" that a width of 16mm will handle 52A for external layers and 31A for internal layers
A second question: is it correct to assume that the total current capacity is the sum of the of the current capacity of external layers plus the sum of the current capacity of internal layers? For example using the above results is it correct to assume that the total current capacity is roughly 160A?
Thanks in advance
 
 http://files.engineering.com/getfile.aspx?folder=0c0efc82-10fe-4798-930b-1b328c16c440&file=layer_distribution.pdf
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1) I have no clue. Never heard of Saturn PCB.

2) Yes, that is the correct assumption the paths all add up. The inner layers will not carry as much because they are going to be hotter than the surface layers so their resistance will be greater.

BTW I'll be amazed if this works.

I would advise you use a specialty board house that can give you stuff like 100mil(THICK) layers and skip the multi-layers.

Keith Cress
kcress -
 
I have designed PCB board to carry up to 80 amps. If your not careful you can make a multilayer board that cannot be soldered with a solder iron. One prototype attempt was a six layer with 4oz on each layer, and it took a pair of Metcal irons and a hot plate and two people to put in some thru-hole components. The eventual production design used a double sided 10 oz for the high currents with a piggy-back four layer 1oz for the control/signal components, and easy to build. To carry current make sure your layer-to-layer vias are a larger diameter than normal vias and use a large number Larger diameters result in more copper surface area and less plating issues for the PCB vendor (better fluid flow through the hole during plating). With heavy copper PCBs staying with larger SMT components is better - 1206 size is desirable, 0603 is not.

Total current is the sum of of all the currents through all of the copper paths. Any shorter paths will carry more of the current since they will have lower resistance if the current is primarily made up of DC currents.

I have seen other alternatives done by others such as 2oz pcbs with copper strip riveted on top and spot-soldered to carry the currents, and custom fabricated bus bars added to a design. Also cheaply made 2.5 KW inverters (140+ amp input at 12VDC) from China that do no more than remove the solder mask and build-up the solder real thick.

Heavy copper board vendors can be found. The information below is from a reply post I made four years ago. I have not rechecked these websites.

The key words for a Google search for PCB boards with more than 2 oz copper is "PCB" and "extreme copper".
(up to 200 oz)
(up to 10 oz)
(up to 40 oz)
(up to 200 oz)
(up to 20 oz)
 
I would also suggest a dual-layer, 4oz. board over a 4-layer 2oz. setup.

Selecting the "plane present" option is not clear in what happens behind the scene. Saturn is not using the plane as a current-carrying device, but it DOES have an effect on what is being carried on the main trace (and in ways I am not familiar with). For example, adding a plane 10mils away increases your current-carrying capacity by 60%... to me, this does not compute.



Keith, Saturn's PCB Toolkit is a freebie that bundles a slew of useful PCB design calculators into one tool. I used it in the past mostly for its impedance calculators to determine trace width/spacing based upon a desired board stackup, but as trace features get small (<15mils) its results begin straying pretty far from reality... at that point I have to pull out a 2D EM solver.

Dan - Owner
URL]
 
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