fine-tuning a clock source

[drgowans]

I am working on a design for removing 2.5 GB/s asynchronous payloads from G.709 OTU1 signals. The payload rate can very by +/- 65 ppm.

I am looking for hardware, or a combination of hardware components, that will take an input clock and produce an output clock at a slightly higher/lower frequency, adjustable in perhaps 1 or 1/2 ppm increments.

The end result is that I need a very low jitter clock that matches the data rate exactly so I can clock it out of a FIFO and send it to a laser output.

Thanks anyone!

 

[logbook]

Look for a VCXO (voltage controlled crystal oscillators).

You may not be able to buy one off the shelf that does what you need. It that case you may need to get a high speed VCO, and a high speed phase comparator to make your own phase locked loop (PLL). Alternatively get a PLL chip with built-in phase comparator.

 

[IRstuff]

Something doesn't sound right. Usually, if there is this type of problem, the clocking is embedded within the data stream itself and a clock recovery circuit is used to avoid trying to get an external clock to properly synchronize.

If you have enough information to use a VCO, then a clock recovery circuit is more appropriate. After all, what are you going to base the oscillator control frequency on? The clock recovery circuit is basically a clock stripper, coupled with a PLL to lock phase and frequency and a buffer to generate the external clock used to clock the data.



TTFN

 

[logbook]

The 2Gb/s fibre optic scheme I was involved with needed a 100MHz ±100ppm tolerance clock at the receiving end in order to drive the SERDES to get the clock recovery to work at all. The local clock was a starting point for the internal VCO/PLL.

 

[drgowans]

Thanks for all your tips. IRstuff, you are right that something doesn't sound right. Generally if I had a stream of NRZ data coming into the design, I would use a clock recovery circuit. That I actually am doing. The OTU1 signal is coming in a laser input and runs through a CDR where we get clock and data.

The problem is in the outputing of the payload. The OTU1 signal contains a payload that uses justification. After stripping out the payload, and because of the tolerances of the justification process, it will come out at a rate somewhere in this range:

14/15 X [Input Clock] +/- 65 ppm

This is the clock used to send data to the output laser. If there is no justification, then getting the clock is easy - I can use a DLL to multiply the input clock by 14/15. It clocks out correctly, and the output buffer doesn't over/underflow. However, as soon as any justification is used, then after several milliseconds, the buffer over/underflows. Hence the need for an adjustable output clock. The underlying payload is asynchronous, but still based on the input clock.

I can't gate the clock, because the output stream can't have that kind of jitter, it is way out of spec. So I need some way of using FIFO levels to fine tune a low jitter clock source to the payload's justification scheme, which will change from signal to signal and perhaps over time.

Mostly I wanted to know if some part out there existed that was easy to finely adjust the clock rate during operation, or if I would have to build something from a few parts, such as a numerically controlled oscillator and PLL, or something along those lines. Any other ideas? Thanks!