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High-Z diff scheme question

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veritas

Electrical
Oct 30, 2003
467
Suppose there is a high-z diff scheme applied to a generator. Since my earliest years I’ve been taught that the require CT kneepoint voltage, Ek, must be at least twice the calculated stability voltage, Vs. Why? I’ve always assumed that it is to ensure that there is sufficient output current from the CT, eventhough satured, to operate the relay. Is this correct?

With an inzone fault, let’s suppose the system contribution is substantially greater than the generator contribution. Thus the CT most likely to saturate (even if only partially) is the line side one. I am unsure as to what exactly happens after fault inception. My take is as follows:
If the line side CT is deeply saturated then it’s magnetising impedance, Xm, virtually becomes zero and it effectively shorts out the load. Deep saturation typically only has spikes outputted from the CT at the zero-crossover points of the primary current (neglecting the phase displacement errors). If the neutral end CT has no saturation then it would drive current through the Rct of the line side CT as well as the relay and voltage limiting devices if any and thus operate the system.

But let’s hypothetically suppose the loadside CT has no output – is the Ek >= 2*Vs to ensure that there is enough line side CT output to operate the system. I’m also mindful of the fact that the CT does not saturate instantaneously.

Anybody shed some more light as to what really happens when an inzone fault occurs and why Ek >= 2*Vs?

 
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CT kneepoint voltage, Ek, must be at least twice the calculated stability voltage, Vs. Why?


It's a general rule-of-thumb that the secondary voltage of a CT for a (symmetrical) 3ph fault be at least half of the maximum rated CT secondary voltage. For example, if we get 200V secondary for a maximum 3 phase, close-in fault - it's a general rule-of-thumb to install a CT that is rated for 400V secondary (or a C400).

Why do this? It's to provide extra margin - 200% margin to be exact. Suppose we had an assymetrical fault with maximum DC component. In this case, our fault current will actually be greater than the maximum symmetrical fault (due to transients i.e. DC component). For this reason, we want to make that the CT can handle the extra fault current without saturating.





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arrehman1

We're talking something quite different here to what you're talking about. With a high-impedance scheme CT saturation is assumed and the CT charateristics are derived based on this pivotal assumption. Applications where no saturation is required would be a biased diff one for example or distance.
 
veritas, you're absolutely right about expected ct saturation assumption for high impedance bus differential. I misunderstood your question XD

- A platform to ASK, LEARN, SHARE, & GROW in power protection, automation, and controls.
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