How does one design a microcoded processor?"

[rowingengineer]

First of all what is a Microcoded processor?

ANY FOOL CAN DESIGN A STRUCTURE. IT TAKES AN ENGINEER TO DESIGN A CONNECTION.”

 

[IRstuff]

Wiseguy... I wonder where you came up with that question ;-)

A microcoded processor is one where the more complex instructions like floating point multiply are actually implemented as a microprogram within the processor core itself. Microcode is, therefore, a programming language for the arithmetic unit within a microprocessor.

TTFN

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[KENAT]

Funny, I was thinking of posting a similar question.

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http://eng-tips.com/market.cfm?

(probably not aimed specifically at you)
What is Engineering anyway: faq1088-1484​

 

[MikeHalloran]

If you list the 8080's opcodes >in octal< and their mnemonics in adjacent columns, then sort on the octal numbers, you will see patterns appear, such that a design for doing the whole thing in TTL almost falls out. Operator, operand, destination each specified by a couple of bits.

If you do the same thing for an 8086, you just see an incredible mishmash; no particular logical pattern emerges. Every opcode appears to be just an offset into a table of vectors to what is likely spaghetti code.



Mike Halloran
Pembroke Pines, FL, USA

 

[DanEE]

a bit surprised also on the general question posted here, when so much information can be easily found on the subject with Google.

As to how they can be built, do some reading on the Finite State Machine as one technique that can be implemented by program logic arrays as the basic building block to control data paths, ALUs and other core functions of a processor.

Microcoded (or picocoded as we called them in IBM) processors have been around for a long time. It was the design philosophy that IBM used to build the System 360 family of mainframes 50 years ago, each with a unique processor optimized to a given level of cost/performance, yet each could run the same instruction set.

The floppy disk drive that became common in early personal computers was a derivative of the early, larger sized IBM 23FD Diskette Drive, the "Minnow" floppy drive used to load the pico code into the mainframe processor as part of the power up process.

The 360 Models 44, 75, 91, 95, and 195 were truly hardwired processors, which became increasingly difficult to do as logic technologies went from disretes to large scale integration.

The core of IBM 3705 communications controller was a hardwired processor as well as one it its high performance line protocol multiplexors.

A truly hardwired processor is a screamer in performance, compared to a pico coded processor designed from the same vintage technology; so not suprisingly the larger 360 models listed above were scientific/research machines of the era. You'll see quite a few Model 75s in 1960's era NASA pictures of their computers used to support the space program.

 

[MacGyverS2000]

row,

I've obviously missed some thread or recent "news" article... care to share so we can all join in the laughs?

Dan - Owner

http://www.Hi-TecDesigns.com

 

[patprimmer]

It was just an inside joke between a few guys. It does not require serious answer.

The joke was something along the lines of, I bet I can find a forum where even if I post an interesting question, no one will notice.

Looks like Row lost the bet. Row, I'll ave a pint.



Regards
Pat
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[CajunCenturion]

[rof]

Good Luck
--------------
As a circle of light increases so does the circumference of darkness around it. - Albert Einstein

 

[patprimmer]

I can't find the original thread that catalyses this thread. Maybe as it was deleted as it also was mainly nonsense.

Regards
Pat
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[CorBlimeyLimey]

Pat,

How can you not find something now the Search function works so well?

Or maybe it was filed in the round bin!

 

[patprimmer]

Search. Dam. I just spent 4 hours scrolling back through every thread I visited in the last 3 months. ;-)

Regards
Pat
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[IRstuff]

As in the case of number of AP exams/graduating senior, a metric, once revealed, winds up perverting itself.

"The 360 Models 44, 75, 91, 95, and 195 were truly hardwired processors, which became increasingly difficult to do as logic technologies went from discretes to large scale integration."

I don't think that's totally true. Certainly, almost all of the first wave of single-chip processors were microcoded. This can be inferred in any processor where a complex instruction takes more cycles than a simpler one. The reason, of course, is that real estate, even on the micro and nano scales, is always expensive, and a microcode machine, while real estate hungry on its own, pales in size compared to a fully hardwired mutliplier. Nonetheless, in any processor where performance is a key parameter, hardwired processing will still dominate. I believe the TI 320C30 had a single cycle floating point multiply, since it's multiply-accumulate loop performance was its raison d'etre.

TTFN

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[MacGyverS2000]

All of the TI320 series chips had single-cycle multiplies, unless there was some oddity in the group.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[IRstuff]

"TI320 series chips had single-cycle multiplies"

No argument, I'm just more familiar with the C30...

That was in contrast with microcoded multiply processors like the 68000

TTFN

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[DanEE]

My memory may be getting hazy, but the early single chip processors were only a gleam in someone's eye in the era of the Solid Logic Technology used to build the IBM 360 computers mentioned above.

A little glimpse into how complex floating point instructions were done, and the performance demands on those instructions compared to the speed of the overall machine can be had in this paper....

http://www.jacques-laporte.org/ibmrd1101E.pdf

Quote:
Introduction
The instruction unit of the IBM System/360 Model 91 is designed to issue instructions at a burst rate of one instruction per cycle, and the performance of floating-point execution must support this rate. However, conventional execution unit designs cannot support this level of performance.The Model 91 Floating-point Execution Unit departs from convention and is instruction-oriented to provide fast, concurrent instruction execution.

The objectives of this paper are to describe the floating point execution unit. Particular attention is given to the design of the instruction-oriented units to reveal the techniques which were employedt o match the burst instruction rate of one instruction per cycle. These objectives can best be accomplished by dividing the paper into four sections-General design considerations, Floating-point terminology, Floating-point add unit, and Floating-point multiply divide unit.

 

[IRstuff]

I was actually thinking two separate threads:

> Hardwired processors survived well into 80s, particularly with the Cray computers, whose ALUs had no registers; every bitpath had to be individually tweaked to get the correct propagation delay to keep up with the other bits in a chunk of data.

> Hardwiring migrated to single-chip microprocessors, particularly those that needed, for example, single-cycle floating point multiplies. In fact, we implemented a Wallace tree multiplier in one particular microprocessor project at work to get performance in the ALU.

TTFN

FAQ731-376
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[rowingengineer]

Thank you to everyone that contributed my first baby step has been made; I will now contemplate the next.

ANY FOOL CAN DESIGN A STRUCTURE. IT TAKES AN ENGINEER TO DESIGN A CONNECTION.”