Looking for 4046 PLL experience

[benta]

I'm working on extracting a clock signal of around 15 kHz using the CMOS 4046 PLL's type II phase comparator.
The type II phase comparator should ideally lock the VCO to the input signal with a 0 degrees phase difference.
The 4046 datasheet always shows a first-order loop filter with one or two resistors and one capacitor

However, thinking back on my theory from 25 years back, a 0 degrees lock ("Type 2 PLL") normally needs a second-order loop filter (my thinking is also based on vague memories of the "Phase-Lock-Loop Design Fundamentals" application note from Motorola, AN535/D). I've unfortunately lost this application note and cannot find it on the web.

Am I right that a second-order loop filter is needed here?

And if yes, can the three-state output from the 4046 to the VCO be considered an integrator, providing the sacond pole for the filter?

Or is the datasheet misleading, so that I really need an active second-order loop filter?

Or is my thinking wrong, is a first-order filter actually sufficient?

Input from people who have worked with the 4046 is HIGHLY welcome.
(answers like "well, I think that maybe...") NOT that much.

Thank You in advance,

Benta.

PS: should someone have AN535/D lying around, I would appreciate a copy.

 

[VEBill]

http://www.everythingrf.com/Uploads/Content/File/Phase Locked Loop Design Fundamentals.pdf

http://www.lansdale.com/Articles/an535.pdf

I'm not sure these are AN535 or AN535/D.

 

[zappedagain]

Oh my..., my 4046 experience is about 16 years old. I believe (uh oh, there it is) your first order filter can still work as long as it introduces enough delay for your total delay to equal 360 degrees. If you can't get that much delay you need to use a higher order. You only pay for it with the lag.

I'm glad VE1BLL had that link. My copies got donated last year when we moved.

Z

 

[benta]

Thank You VE1BLL, those are exactly what I've been looking for.

Reading through the note, my suspicion has been confirmed:
an active loop filter is indeed needed to get a Type 2 response (0 degrees phase error).
I'll design accordingly.

But I find it depressing that both data sheet and application notes (both for 4046 and 74HC4046) are so "mealy mouthed" on this point

Best Regards,

Benta.

 

[benta]

A little update on this issue.
I ordered Floyd M. Gardner "Phaselock Techniques", since everyone refers to his work. I have now read it through and come to the following:

To get a type-2 response (2 poles at zero, corresponding to 2 integrators in the open loop transfer function) you indeed need either:
1: an active loop filter
2: a passive filter, but in a completely different configuration than shown in the 4046 datasheets and appnotes.

In short, the 4046 datasheet sucks!

I chose the active filter solution, prototype PCBs are ready next week, I'm interested to see the measured results.

Best Regards,

Benta.


PS: the Gardner book is not cheap, around 65 Euro. However, I have no problem paying that amount for over 40 years of experience and knowledge on PLLs. There are other books where I won't even pay the paper price, as it's been destroyed by the ink...

 

[geekEE]

You might also look at "Phase-Locked Loops: Design, Simulation, and Applications" by Roland E. Best. It's a good book and it comes with a CD that has an application to help analyze and design PLLs. The application doesn't do anything that you couldn't do with MathCAD or Excel, but it's useful for quickly trying some different types of filters.

One caveat about the software, which is that the installer does not run under 64-bit Windows 7. However, once it is installed (I used Windows XP compatibility mode), you can copy the folder somewhere else and run the application under Windows 7.

Glenn