In general, I put the GND layer directly under the top component side and VCC under the bottom solder side.
I've usually used split power planes to minimze layers. Steve Smith
Product Engineer
Staco Energy Products Co.
Usually in a multilayer design, it's best to place VCC and GND planes where they have the least likelihood of being damaged. For me, that means the interior layers (3-6).
Though some design have no issue with durability, I caution against placing plane layers near the top or bottom because long term vibration effects can cause shorts or opens.
> I'm interested in how vibration causes shorts near the outside layers but
> not on the deep inside ones. Could you explain this further?
... has a simple yet not-so-obvious answer.
A defense contractor's (high density BGA) board I recently put through the shakes had a power and ground plane scheme like the type you suggested -- near a surface layer. The shorts arose at the board's mechanical mounting points to the system in which it resided (the hole-plane clearances on this particular board were too tight for the board's inertial mass).
What happened is the mounting screws eventually wore away the FR-4 covering the surface plane layer, which happened to cover the VCC plane. This was exacerbated by the metal washers this particular contractor had chosen. It was only a matter of time before the VCC plane shorted to case ground via the mounting screws.
Once nylon mounting screws were inserted, a second vibration test with the same type of board revealed plane-to-trace shorts forming near the BGAs and other large parts. These generally did not form, however, until g-forces were sufficient to vibrate parts off the board (about 30 grms and up), at which point layer integrity started breaking down.
From these lessons, as a design rule, I put at least 0.2-in. total circuit exclusion around my PCB mounting holes, and place my plane layers closer to the board interior -- whether my design will take serious punishment or not.
In response to the sequence of layers.
If the board contains high frequency signals I would make layer one the signal layer placing all the controlled line widths on this layer(IE 50 ohm lines, etc.) The second layer is the ground layer with the distance from the top layer specified to meet line characteristic impedences. Layer 3 is a signal layer, layer 4 is the VCC layer,layer 5 is signal, layer 6 is either VCC or Grd. ,layer 7 is signal, and layer 8 is the reverse of layer 6. Having alternate layers of full copper will also reduce warping problems.
