A PIC is the standard solution. Their 8-leggers come to mind. What frequency or frequency range do you need? There are lots of app notes on the web. Make google your friend.
You really want a 2-bit gray code generator. Xilinx has a nice N-bit generator VHDL template in their ISE software that is a free download:
Gray code w/ CE and async active high reset
-- Usage of Asynchronous resets may negatively impact FPGA resources
-- and timing. In general faster and smaller FPGA designs will
-- result from not using Asynchronous Resets. Please refer to
-- the Synthesis and Simulation Design Guide for more information.
<next_binary_count> <= <binary_count> + 1;
process(<clock>,<reset>)
begin
if ( <reset> = '1') then
<binary_count> <= (others => '0');
<gray_count> <= (others =>'0');
elsif ( <clock>'event and <clock> ='1') then
if <clock_enable>='1' then
<binary_count> <= <next_binary_count>;
<gray_count> <= (('0' & next_binary_count(<width-1> downto 1)) XOR <next_binary_count>);
end if;
end if;
end process;
You can simplify this down to a two bit counter and a couple of XOR gates if you want it in CMOS hardware.
