RESET Signal

[IAEA]

Hello to everybody.

I would like to ask to the foro a question regarding RESET.

I know that in a computer, when you introduce a reset signal, the normal required confirmation time is about 500ms but my question is what would happen with a equipment based in FPGAs when you introduce a reset signal. I asked to some friends and they told me that I would need a debounce of 4ms.
Is this a reasonable (normal) time?

Could someone help me with this confirmation time? I don't know the magnitude order of this time and need an estime

Thank you in advance

Best regards

 

[IRstuff]

http://www.noels-lab.com/datasheet/NL1001.html

BUT, your mileage may vary. Why not just use 0.5 s? Is it that time critical? If it is, why aren't you measuring the bounce time on YOUR switch?

TTFN

 

[nbucska]

The FPGA may need time to configure AFTER the reset
so you may have to generate two different reset signals

<nbucska@pcperipherals DOT com> subj: eng-tips
read FAQ240-1032

 

[Comcokid]

Back in the old days of microprocessors, some required reset to be at the reset state of a certain amount of time, otherwise not all the internals of the uP would be reset properly, and the unknown state would result in unpredictable operation. Nowdays, most uPs properly react to any reset and reset to a known state regardless of reset length.

Now, a FPGA which has one of the I/O programmed as a reset for the internal logic may require a reset of a certain length, depending the internal programming, when the reset is clocked, when the resulting reset signal acts upon any registers, flip-flops, adders, etc.

The state of the reset input may only be sensed on the rising or falling edge of a clock signal also going to the FPGA.

 

[felixc]

nbucska is right, some FPGAs need their own shorter reset signal while the rest of the system gets a longer one, while the FPGA gets its internals loaded fromn an external prom.

This is not what you want to read, but all in all, there is no magical number for the duration of a reset signal. It is dependent of your system design.

 

[walker1]

Another reason for the long reset could be to 'kill' any content in dynamic RAM.
If that is, the RESET signal also holds the refresh circuit.

What good that might do, however, I am not sure.

In the old DPMI (DOS Protected Mode) days, you could switch into DPMI by a CPU instruction, while returning to DOS required a short reset pulse. That you got by calling some BIOS function and a special hardware circuit.

The 'normal' reset, however, was much longer.

 

[Warpspeed]

Reset is required to be held down only long enough for everything within the system to start up in an orderly fashion.

Often the slowest thing to get moving is the crystal oscillator, and once that has reached full amplitude the system may then need many subsequent clock pulses to initialise some internal functions from microcode at start up.

On the other hand a system of fast logic gates and flip flops in an FPGA may only need a single very fast reset pulse to clock everything to a known state simultaneously.

It all depends on what it is, and what reset actually does. If a 500mS reset time is specified, you can be sure there is a reason.