homoly
Electrical
- Jun 11, 2007
- 100
Hello,
I would need some advice with one problem related to clock signal picking up noise.
First the layout. The source of the clock signals ( actually 2 identical clocks which are complementar to each other and are selected by logic ) is gated 555 output of 22kHz by CMOS AND gate. The target of the clocks are CMOS inputs of the CLK of CD4013 D-type flip flop.
As the PCB containing the 4013 flip flops is a "patch" to existing design so unfortunatelly I have to route the clock signals to target PCB from the source PCB with a quite a long wire of 70cm.
First phenomena I have observed on osciloscope is that after a nice clean pulse train of the clocks I got a series of pulses which have a sag on the top. I assume this is due the fact I have not performed any kind of impedance fitting between the two interconnected PCBs and I have connected the output of the CMOS and gate with the CLK CMOS input of the 4013 flip flop directly through a wire.
Second phenomena I have observed is if I am swapping the clocks quickly ( f.e. the clock1 is feeding FF1 CLK for 10 seconds than it is terminated for 10 seconds and than again restored ) cycling in this way tends to result in building up distorsion of the clock signal I am measuring at the clock input of the D-FF. I have found in one book in the case of long clock lines ( I do not know if I can consider 70 cm wire for that ) the output of the CMOS should not be connected with the CMOS input directly but it should be terminated by some resistor as "resistor buffering" but I did not found more description on this. Could somebody give me more information on this concept how does the resistors should be connected and what is the philosophy of the resistor value selection?
Any advice is very appreciated.
Gabriel.
I would need some advice with one problem related to clock signal picking up noise.
First the layout. The source of the clock signals ( actually 2 identical clocks which are complementar to each other and are selected by logic ) is gated 555 output of 22kHz by CMOS AND gate. The target of the clocks are CMOS inputs of the CLK of CD4013 D-type flip flop.
As the PCB containing the 4013 flip flops is a "patch" to existing design so unfortunatelly I have to route the clock signals to target PCB from the source PCB with a quite a long wire of 70cm.
First phenomena I have observed on osciloscope is that after a nice clean pulse train of the clocks I got a series of pulses which have a sag on the top. I assume this is due the fact I have not performed any kind of impedance fitting between the two interconnected PCBs and I have connected the output of the CMOS and gate with the CLK CMOS input of the 4013 flip flop directly through a wire.
Second phenomena I have observed is if I am swapping the clocks quickly ( f.e. the clock1 is feeding FF1 CLK for 10 seconds than it is terminated for 10 seconds and than again restored ) cycling in this way tends to result in building up distorsion of the clock signal I am measuring at the clock input of the D-FF. I have found in one book in the case of long clock lines ( I do not know if I can consider 70 cm wire for that ) the output of the CMOS should not be connected with the CMOS input directly but it should be terminated by some resistor as "resistor buffering" but I did not found more description on this. Could somebody give me more information on this concept how does the resistors should be connected and what is the philosophy of the resistor value selection?
Any advice is very appreciated.
Gabriel.
