Scrambled clock / data....

[melone]

Could someone please explain that basic concepts involved in scrambled clocks / data? I am currently involved in trying to reduce EMC emissions on some PCB's and have heard that scrambling the clock can produce approximately 24dB noise reduction! Also, approximately how much jitter can I expect on a scrambled clock?

 

[jsolar]

This is tricky business. First, you must not have any UATS, PLL's or data modem devices involved. They have specific clock requirements. Second, you will be slowing things down. Since you cannot violate any min timing rules, you cannot increase you clock. So you are left with decreasing the clock in a controlled pseudo random manner. If you do not have analog control over your clock, you are left with digital changes. A large reduction in your average clock rate can give you good suppression. A gold code or CDMA like pattern can give you best results, but you will have a lower average clock rate and possible latency issues. You can dither analog and reduce your peak noise, but remember that your are increasing your overall EMI, but your worst case gets much better.