STEP UP/STEP DOWN RAMP GENERATOR

[jorgemoreno]

Hi everyone,

I have an unusual application in wich I need one Output (OUT1) and two input signals (IN1 and IN2)in a circuit, the input signals will provide +V (+24V) or will be open (lead lifted not grounded) depending on certain conditions:

1. IN 1 = +V, when this happen a Step Up voltage ramp is generated at a rate of 1V/sec until it reaches +10 V approximately, when IN 1 is not longer applied with +V (input open) the voltage reached (+10V) must remain until the input conditions change.

2. IN 2 = +V, when this happen a Step Down voltage ramp is generated at a rate of 1V/sec until it reaches 0V, when IN 2 is not longer applied with +V (input open) the voltage reached (0)V must remain until the input conditions change.

I have experimented with a circuit using a PNP bipolar transistor arranged as a constant current source charging a Capacitor (IN1), this gives me the step up ramp with no problem at 1V/sec, the inconvenience of this is that I have to provide negative voltage on transistor base to operate it, this obligates me to use a negative source on the application which means to add more investment and circuitry. Besides when trying to dicharge the capacitor using a second transistor (NPN)as IN2 the step down ramp does not act in the same way as the ramp up, the difference is the time constant even I am using same resistor values.

If someone could help me to find out this application I will be really grateful.

Thanks

Jorge

 

[nbucska]

Add desired timing diagr. of IN1,IN2,out, too.


<nbucska@pcperipherals.com>

 

[jorgemoreno]

Thanks nbucksa, I have the timing diag how do I add it, sorry but I am new to eng-tips.

 

[IRstuff]

I assume that you're buffering the output of the ramp generator, so why not simply run both inverting and non-inverting amplifiers to the ramp? You could offset the input enough so that an analog switch will select the different amplifier outputs as desired.

In fact, there's no reason why you can't use an NPN current source and swap the sense of the amplifiers.

TTFN

 

[nbucska]

The ramp is very slow -- 1v/sec for 110 sec's -- and "it must remain..." so :

I would use digital circuit : input --> comparators--> (start logic if needed ) --> up/dn counter --> DAC . Select osc. frequency, DAC resolution etc. to satisfy specs.


<nbucska@pcperipherals.com>

 

[jorgemoreno]

Thanks IRStuff I willwork on your tip, everyone: IN1 and IN2 are exlusive, means that when IN1 is activated ramp is going up and IN2 is not present, when IN2 is activated ramp is going down and IN1 is not present, based on IN whenever they reach their correspondig target they will remain on that value unless the IN conditions changes, in other words if IN1 is activated and then turn off with IN2 also off the output will be +10V until IN2 is activated and ramp down starts and viceversa. My email in case you want to send a drawing which will be really appreciated is jorgea_moreno@yahoo.com Thanks in advance for all your contributions.

JM

 

[nbucska]

Please check if I understand correctly:

When IN1 goes from 0 to 24V : it starts to ramp up
at 10V it stops
When IN2 goes from 0 to 24 V : it ramps down, at 0 is stops.

Any other change won't affect the ramp generator.

I E-mail the circuit.


<nbucska@pcperipherals.com>

 

[jorgemoreno]

Yes, you are right, any other change won't affect the operation nbucksca, let me check the circuit you just send me. tks

JM

 

[nbucska]

I have difficulty with scanner, will wire list be OK ?


<nbucska@pcperipherals.com>

 

[jorgemoreno]

Yes nbucska wire list will be ok to give it a try, if a doubt arises I will posted for your help.

 

[nbucska]

sending it.

<nbucska@pcperipherals.com>

 

[jorgemoreno]

Hi nbucska, which software you used to simulate circuit? I am having trouble interpreting files you send me one seems to be truncated. I you could email me directions to interpret how to build it from node list i will aprecciated.

JM

 

[jorgemoreno]

IRStuff I wonder if you can provide more details on your comment to work it out. Thanks

 

[nbucska]

I haven't simulated it. I faxed schematics, is it good enough?

<nbucska@pcperipherals.com>

 

[IRstuff]

ramp output goes to non-inverting and inverting amp.

output 4 to 1 mux selects between:
non-inverting output
sample-hold of non-inverting output
inverting output
sample-hold of inverting output

ramp is discharged
4:1 mux selects non-inverting output; output is 0V
ramp up; output starts ramping up
ramp reaches 10V; output reaches 10V
4:1 mux selects sample-hold of non-inverting output; output stays at 10 V
ramp is discharged; output stays at 10V
4:1 mux selects inverting output; output stays at 10V
ramp up; output ramps down
ramp reaches 10V; output reaches 0V
4:1 mux selects sample-hold of inverting output; output stays at 10V
ramp is discharged; output stays at 0V
4:1 mux selects non-inverting output; output stays at 0V



Something like that. It's a bit of a gludge, but allows you to use the same ramp with the same timing and linearity for both up and down ramps.



TTFN

 

[nbucska]

IR:
One NPN current source won't do it -- you need to ramp down, too, with the same slope. You could use a
voltage reference -- both + and inverted i.e. - )
switched to common integrator.

The hold time ( at 0 and 10 V ) is not specified, may be
too long to realize it by analog due to leakages.

Accuracy is hard to satisfy and maintain.

I submit digital with DAC is better and easier -- even if
it takes more circuitry.

<nbucska@pcperipherals.com>

 

[IRstuff]

That's why the ramp is discharged before switching to the inverting output.

Obviously, the inverting output needs a 10V input offset to put the ramp 0V at 10V output, so when the ramp goes up, the output of the inverting amp goes down toward 0.

Since the poster has not specified hold times, accuracy, linearity, etc., there was no reason to assume any limitations on the circuitry.

TTFN

 

[jorgemoreno]

Hi

Hold timemay vary, it could be 1 sec to anytime, the rule is if I start IN1(ON), ramp goes up from 0V to 10V when IN1 (OFF) 10V are hold until IN2 is activated (ON) and ramp down from 10V to 0 V, the slope going up and down is the same 1V/sec means that after tens steps i will reach 10 V if I ramp up or I will reach 0V if I ramp down, both input are exclusive meaning that IN1 will never be activated at the same time with IN2 is one or the other. Linearity when ramping up or down must be, accuracy I may allow +/- 2% of error.

JM

 

[IRstuff]

Given that choice, NBUCSKA's solution is probably the easiest to integrate and implement. All you're asking for is less than 10 bits, which is trivial.

You could probably get a serial DAC with a simple FPGA to run the logic.

TTFN

 

[nbucska]

You can get cheap (time-) clock xtal for 32K - this needs
1 bit counter. You can use 8,9 or 10 MSB-s.

If you have a computer in the system, IRSTUFFs FPGA
suggestion may be worth considering -- otherwise you
need a PROM for programming the FPGA.




<nbucska@pcperipherals.com>