Theoretical Question - High current + FETs

[ryandias]

I am a mechanical designer, definitely not an EE.

I have been running some thermal/current flow simulations on a concept we are working with, and cannot explain some of the results. Chatted with two EE's and had no better theories.

The most basic equivalent circuit is as follows:
Buss Bar - Grounded on the left hand side.
4 semi equally spaced FETs mounted to the buss bar.

GND _____FET1_____FET2_____FET3____FET4

I injected 100Amps into each FET.

The simulation resulted in FET 1 heating up much more then FET4.

I looked at the left to right current density and noticed in the FET layer that there was some in FET 1 and a tiny bit in FET2 and virtually none in FET3&4.

The FET resistance i set to greater then 10x the bus bar resistance. I don't understand why the current would choose a higher resistance path?

My theory is that the greater current density in the FET 1&2 explains the higher temperatures

I am open to any other theories or explanations?????

 

[IRstuff]

No, you claim to have "injected" 100 A into each FET, so they're seeing the same current. But, what gate voltage are you using, what threshold voltage, what drain-source voltage are you seeing, what's the voltage drop along the bussbar?

It's hard to give cogent answers to an incompletely specified problem.

TTFN

FAQ731-376

 

[melone]

Is the ground on the left, actually a connection point to your power source? If so, won't you have 400 amps going through that point? If so, that point will be hotter that near FET4, right?

 

[DRWeig]

Yes -- more info, please.

Measure voltage across each FET junction with all currents flowing, and also measure voltage drops from each FET to the power ground. I think it'll be enlightening. That's enough current flow to guarantee some voltage drop along the ground path.

Good on ya,

Goober Dave

 

[ryandias]

FET voltage top to bettom is 0.1V
Rds is about 0.001ohm

We looked at power dissipation and the Power for each fet was with in 10%. (voltage x current)

(Please remember I have only mechanical background)

I added a boundary condition to the top surface of the fet; this being 100amps in.

The resistance of the fet was calculated in accordance with the data sheet, and a linear relationship was defined for this Rds on. Should help in current sharing - model started with plus and negative buss bars.

in trying to simplify we moved to just a ground buss bar and injecting current into the fet (defined as a volume/cube with appropriate Rds on) We are trying to see the coulombic heating.

 

[IRstuff]

I'm confused, are you modeling transistors or are you modelling some fictitious volume?

I'm now questioning your "most basic equivalent circuit" since it appears as if each FET is actually in series with the others and not in parallel.

What is the resistance of the bussbar? How is that actually modeled in your model?

TTFN

FAQ731-376

 

[ryandias]

For reference.

First is the Self Heating I am observing.

Current Density

 

[Warpspeed]

Yes more info please.

The FETs may have equal current(?) But do they also have equal voltage source to drain? To do that, the drain busbar probably needs to have the power connection at the right hand end, next to FET4.

It is rather like the reverse return header concept frequently used in pipework to ensure equal flow through many parallel branches.

 

[IRstuff]

Even if that were done, if the gate voltage is only marginally above the threshold, the ground bus drop would have an impact on the drive to each device.

TTFN

FAQ731-376

 

[Warpspeed]

One would hope that the gates are all driven sufficiently to at least turn the beasties on !!!

Another thought. I guess we are all assuming this is a dc circuit. It may be operating up in the Mhz region. In which case, all bets are off as regarding layout and parasitics.

 

[ryandias]

ok, you guys are thinking about this way to realistically.

I have simplified it emensely to put into the initial simulation.

We have 5 solids (volumes);

1) busbar - approximately 100mm long, 18mm wide, and 0.35mm thick.

2,3,4,5) FET tabs - 8.5mm long, 7.3 wide, and 1.2mm thick.

I did not include any type of solder.

The top surfaces of each fet have a boundary condition of 100A into the surface. (each fet = 100A)

The only heating I am concerned with is the self heating due to the resistance (Rds-on) defined as per data sheet with a "piece wise linear" relationship.

The gates have nothing to do with this "simulation". (But yes we do have resistors between the gate drive and each gate pad)

The current is applied for 0.4 seconds

The ground is defined as a 3mm hole on the left side of the busbar. (inside surface defined as my ground)

The voltage drop each fet see's across its body is within 10% of its friends. I am happy with this.
Currents each fet see's is DEFINED as 100A.
So theoretically the power dissipated in each fet is "Similar".

Now my question arrises because I see a large change in self heating.

On a side note: I changed the ground definition to a "North" side of the busbar (if east was the old ground side) and allowed that whole long surface to be ground. This change resulted in both outter fets heating more then the inner ones. I think because more current area (fets are somewhat more central - giving outter fets more "ground")

But back to the original question. Could the current seen inside the busbar affect it's path? I suggested that because the current density gets higher as the flow passes each FET, by the time the 4th is near, it is so Dense, that it may choose to "detour" through the fet body - even though it is a higher resistance.

My EE collegues do not agree with this theory.

 

[IRstuff]

You need to look at, if possible, the distribution of current within the bulk of the materials. Resistance can be tricky to properly model in 3-D, since current ALWAYS takes the path of least resistance. When the current is not uniformly injected or extracted from a 2-D or 3-D object, you get localized current crowding, which can signicantly affect your heat distribution and effects.

For example, the outer FETs are dumping current into the ground buss from one-side only, whereas the two in the middle have ground buss on both sides. This will cause the current in the outer FETS to crowd inward, increasing the current density at the junction with the buss bar, which will increase the heat dissipation, since the outer parts of the outer FETs bulk is not helping in current conduction.

You might look up "spreading resistance" or "current crowding" to get some references to look at.

TTFN

FAQ731-376

 

[Warpspeed]

The gates may have nothing to do with the simulation, but that can sure become a pretty critical consideration in a real circuit.

As IR stuff says,insufficient gate turn on voltage can make a substantial difference to Rdson. There is also the distinct possibility of high frequency oscillation occurring unless precautions are taken.

O/k I think we all have a clear enough picture of the source side, your busbar and the single 3mm screw holding together a 400 Amp connection. But what is attached to the four drain connections?

 

[jimkirk]

Hmm... is your bus bar copper? Nice low resistance,

0.0000000168 ohm-meters

cross-sectional area 0.063 cm^2
length between last FET and "ground" about 2.5 cm

Resistance about 0.000067 ohms

Power @ 400 amps about 10.7 watts in that section of bus bar. I'd be concerned with that heating in my model as well as the 10 watts per FET.

 

[kf2hi]

In the configuration stated in your original post, with the ground on the left:

Under fet1, you have 400 amps flowing through the buss.
Under fet2, you have 300 amps.
under fet3: 200 amps
under fet4: 100 amps.

The heating (power) varies with the square of the current.
So the current through the buss under fet1 generates 16 times the heat generated under fet4.
Naturally the buss gets much hotter on the left.