Based on JEDEC JESD51-7, defining the PCB as 4 layer 2x 2oz and 2 x 1oz (inner) with copper area 70mm x 70mm. It is used as high conductivity test bed for package thermal performance assessment.
I'm interest in transient and wish to know if anyone calculated or/and measure thermal capacitance (as well as JESD51-3). Is this validated?
You may modify them to include thermal vias (for exposed pad package such as QFN or TSSOP28 or DPAK).
I'm interest in transient and wish to know if anyone calculated or/and measure thermal capacitance (as well as JESD51-3). Is this validated?
You may modify them to include thermal vias (for exposed pad package such as QFN or TSSOP28 or DPAK).
