What does this error message mean during constrain attempt 2

[Aubreyair]

I am new to Catia V5 and in the process of creating a parametric assembly.
This is one of the many problems I have encountered.
Loop design between geometry and constraints.
Can anyone tell me what this error means exactly and how I may get around it.

 

[CPosner]

This is best described with a tree....
but

Loop design is exactly that...You make and external reference to Part A from Part B. You get the loop error when you then try to make an external reference to Part B from A.

You need to be careful and manage your external references.

One way to get around this is to create and wireframe and create your references individually to the wireframe. Wireframe is at the top. In other cases where one part must reference another, just be concious of what your are doing and know the dependencies.

Hope that helped you out...good luck!