AD7730 - latching-up ?

[KWOL]

Hi,
I am using an AD7730BN and a strain-gauge with sensitivity 2mV/V, so the input voltage range is -0..10mV with 5V excitation. Active channel: IN1+AIN1-;

After setting up DAC and FILTER regs, applying full-scale int. calibration, the content of the gain register is insignificantly changed, but after 0-scale int. calibration, the content of the offset register is 800000 - as before calibration. After that the part is set in continuous convertion mode. After each falling edge of RDY, the data register is read, but it always is FFFFFF, independently of the input range, chop/nonchop mode or any other settings. The contents of DATA reg is FFFFFF even on the beginning - after raising edge on RESET.
Does it seem the part is demaged or is there something, that I shall take care of? I suspected that the data register was latched-up due to the power sequencing (DVDD and the system digital circuitry is powered up before AVDD), however, I used 47ohm resistors in serial with all digital inputs/outputs to avoid excessive currents. Maybe it is not enough?
What would you suggest?
Is there anybody, who would help me?

Regards,

KWOL

 

[stefandk]

AD7730 AVDD can be turned on after DVDD. In my design AVDD (5V) is turned-off in power-minimizing mode and turned-on again, when key is pressed(VDD=3.6V). All IO wires are trough 470 Ohms passed. In my oldest design no resistors are used (but AVDD is tied to DVDD=5V). In oldest design
i have one (i cannot remember what exectly) problem with ADC and decision was : DATALINEtoADC was drived to low, even
when data is readed ( trough otrher dataline). I do not why,
but in default design this code is not nessesary.
Another thing - in weighscale , which we produce, selfcalibrating of ADC is not used ( i can't remember why).
Latching (and preheating ) of chip i have see , when AGND is
not tied to DGND.

 

[microindus]

hy
have your resolve this problem?
if no, i can help you if you send me your schema :
Micro-indus@voila.fr