CMOS noise

[zappedagain]

I'm just curious what you think of this one. I have a 3.3V CMOS 60 MHz clock, and this is what it looks like with a 500 MHz probe (spec'd to have <14pF capacitance, and other tests show the rise and fall time of the probe/scope are better than 1.5nS).

http://files.engineering.com/getfil...cb-8120-625a17bd89b9&file=LCLK_at_U52-J20.PNG

I'm thinking that looks reasonable, there might be a bit of reflection distorting the edge, but it is still monotonic.

Here is what my worst case board level simulation shows:

http://files.engineering.com/getfil...28a-1d967f7c2ead&file=LCLK_at_U52-J20_sim.PNG

So my question is... Is this 0.3Vpp of ripple on the edges worthy of concern? Or is it far enough below (VIH-VIL) (2.0-0.8-1.2Vpp) that I shouldn't be concerned with it?


I'm chasing a problem where a FIFO forgets to shift all the data out, so following packets are shifted, and eventually the problem will occur again and the data gets shifted even further. This only happens every couple of days, so I'm looking at about 1 out of 10^13 cycles of this clock if it is really the root of the problem.

Thanks,

Z

 

[itsmoked]

I feel for you looking at a 1 in 10^13 issue..

What device?

Keith Cress
kcress -

http://www.flaminsystems.com

 

[zappedagain]

PLX PEX8311. It translates a local bus to a PCI bus to a PCIe bus in the computer. Two die, one IC, so the PCI bus is internal. Lots of fun.

 

[itsmoked]

Looks like fun.. 300+ pins. <Shudder>


If that simulation is close to true with that saw toothed edge, I would expect you to have issues. It could be you don't see them with your scope.

Are the rise and fall times within the chip's requirements?

There's no software checksums etc. in your application to ferret out a problem and support correction?

Keith Cress
kcress -

http://www.flaminsystems.com

 

[IRstuff]

If the scope trace and sim are close to correct, then you do ave potential problems:
> setup times -- your scope traces seem to be a low-pass version of your sim, and possibly marginal on setup time. Your rise and fall times appear to be substantially worse than one would expect for such a frequency. Typically, one would want no more than 25% of the duty cycle devoted to transition time. Your scope traces show almost the exact opposite.

> Your sim shows noise that your probe can't see. Often, ripples at the clock threshold can cause odd things to happen, like metastability

TTFN
faq731-376

 

[zappedagain]

I'm believing the simulation results. A FFT of the scope trace is showing a minor peak near 900 MHz, right where any T-line reflections would occur.