zappedagain
Electrical
- Jul 19, 2005
- 1,074
I'm just curious what you think of this one. I have a 3.3V CMOS 60 MHz clock, and this is what it looks like with a 500 MHz probe (spec'd to have <14pF capacitance, and other tests show the rise and fall time of the probe/scope are better than 1.5nS).
I'm thinking that looks reasonable, there might be a bit of reflection distorting the edge, but it is still monotonic.
Here is what my worst case board level simulation shows:
So my question is... Is this 0.3Vpp of ripple on the edges worthy of concern? Or is it far enough below (VIH-VIL) (2.0-0.8-1.2Vpp) that I shouldn't be concerned with it?
I'm chasing a problem where a FIFO forgets to shift all the data out, so following packets are shifted, and eventually the problem will occur again and the data gets shifted even further. This only happens every couple of days, so I'm looking at about 1 out of 10^13 cycles of this clock if it is really the root of the problem.
Thanks,
Z
I'm thinking that looks reasonable, there might be a bit of reflection distorting the edge, but it is still monotonic.
Here is what my worst case board level simulation shows:
So my question is... Is this 0.3Vpp of ripple on the edges worthy of concern? Or is it far enough below (VIH-VIL) (2.0-0.8-1.2Vpp) that I shouldn't be concerned with it?
I'm chasing a problem where a FIFO forgets to shift all the data out, so following packets are shifted, and eventually the problem will occur again and the data gets shifted even further. This only happens every couple of days, so I'm looking at about 1 out of 10^13 cycles of this clock if it is really the root of the problem.
Thanks,
Z