CT saturation in a high impedance scheme

[cesgibis]

Hi,
When an internal fault occurs in a high impedance differential protection (whether REF or bus bar),the voltage across the relay can reach high levels, because the CTs are supposed to force their secondary currents into the high impedance branch.
1) But does this push the CTs into early and very quick saturation, the burden of the CTs being very high in this case ?
2) and when in saturation, normally the output of the CTs is close to zero. so how does the relay trip of no current is generated by the CTs. Also a saturated CT has a very low magnetising reactance (close to a short circuit) so the voltage across the High impedance module is non-existant. So how does it trip ?
Thanks for your assistance in understanding this.

 

[stevenal]

I suggest you go to selinc.com, register (free), and download the 587Z manual.

 

[jghrist]

High impedance differential relays are fairly tolerant of CT saturation.

 

[inpran]

@cesgibis:
1. For an internal fault, as pointed by you

"When an internal fault occurs in a high impedance differential protection (whether REF or bus bar),the voltage across the relay can reach high levels"

The fault current will enter the high impedance circuit resulting in raise in voltage. The relay will issue a trip based on this voltage. Further, calculation of this voltage setting will be carried out considering the saturation voltage of the connected CT cores and the CT lead resistance and thus, as clarified by jghrist, the protection will be fairly tolerant of CT saturation as should be the case.

2. Now, for a through fault if one of the CT is driven to saturation, you have already pointed out that no voltage will be appearing across the relay and hence there will not be any trip.