Current Regulation on a Buck DC Converter 1

[joelg11]

I'm an entry-level engineer, and I have a design question for the forum:

I'm designing a multiphase buck DC/DC converter which will convert roughly 65VDC to 52VDC at up to 150A. I'm using 4 phases, so inductors, etc will be designed to about 40A/phase, MOSFETS will be paralleled for less (about 13A)current, but that is unimportant.

The crucial point where this design deviates from the common design is that it is essential that we have current control rather than just a current limit. An external analog comparator signal is to dictate the current setpoint. I'm really wanting to use two Linear LTC3860 controllers, but again they only provide a current limit. Another option is to do a custom design using a PIC microcontroller, but I still need help with how to use the current sense circuit to control the PWM to provide current regulation.

Anyone have any ideas? I attached a rough schematic of one of the stages, with the current sense signals going off-sheet to my theoretical controller.

Thanks for your help!

 

[VEBill]

One minor point is that the transformer secondary circuit has a one-wire output (return missing). I suspect that's not going to work as drawn. This doesn't imply that this is the only problem. It's just the one that jumped off the page at me.

150A power supplies are a tall order for a fresh engineer. Good luck.

 

[djs]

You might look into cascaded loops. Inner loop controls voltage, outer loop controls current.

 

[Warpspeed]

Another totally different and less usual approach might be a ripple regulator.

Basically this switches on and off as the current through your buck inductor rises and falls between two set thresholds.

Suppose you wanted to set 40 amps average constant load current with 4 amps peak to peak ripple (in one phase). When the current through the flywheel diode and inductor falls to 38 amps, you turn on your FETs.

When the current through the FETs and inductor ramp up to 42 amps, the FETs switch off. The whole thing self oscillates to provide a constant amplitude peak to peak output ripple symmetrical around the desired average dc output current.

Current limiting is very fast and inherent in the strategy. Only difficulty with this might be that the switching frequency will vary considerably with load variations, and that feature may be objectionable.

But ripple regulators are very simple, respond very quickly to sudden line/load voltage changes and offer an interesting alternative.
It probably offers the fastest responding constant current switching supply you can build, because the speed of response is limited only by the stored inductive energy.
A second LC filter stage can reduce the actual final output ripple to well below what the ripple regulator stage itself needs to function.

How to do this with multiple phases is something I have not really thought through.
But it may be possible to phase lock four in quadrature by very slowly shifting the current sensing threshold of three of the phases in the manner of a phase locked loop.

The whole thing would probably briefly break out of quadrature lock to respond to sudden step load changes, but I cannot see that being a serious disadvantage compared to the advantage of speed of response to said step load change.

 

[VEBill]

Suggestion: Consider RF emissions and FCC approval early.

 

[joelg11]

Thanks all for the responses:

Warpspeed, great response - I'm looking at ripple regulation circuits right now. This is an unusual design as well - because output current ripple is not the concern so much as ripple current seen by the source (think battery or fuel cell - current source). So a follow up question is - and maybe this is a dumb question, but is current ripple regulation the same on the input and output of a buck converter? Will regulating the output current to +/-2% also have the same effect on the input side, since the converter is essentially pulling current through to the load?

 

[MagicSmoker]

Hi Joel...

This would be easy if it weren't for the current level.

First off, you don't use the current limiting function of a switchmode regulator chip to regulate current - it's strictly for protecting the switch. You use the error amplifier for this job. Whether you regulate voltage, current or some combination depends on where you get the error signal from in the first place. So if you want to regulate output current you sample the current; if you want to regulate output voltage then, yes, you sample the voltage. Either use a shunt (with a high side amplifier or instrumentation amp, depending on the accuracy needed) or a Hall effect device. If, for example, the error amplifier uses a 2.5V reference then you need to amplify the voltage produced by the shunt (or Hall effect device) to 2.5V when the maximum current is reached.

The buck converter is an intrinsically stable topology so nothing exotic needs to be done to close the loop.

Nothing particularly complicated about multiphasing but you would do well to read this most excellent article on them:

http://www.eetimes.com/design/power...efits-of-multiphasing-buck-converters--Part-1

It explains how input and output ripple is affected by the number of phases.

I STRONGLY suggest you build a single phase prototype first. Also, expect to require 4oz Cu (140uM) FR-4 board to carry this sort of current.

Another name for what Warpspeed suggested is called a "bang-bang" regulator, btw.

NB: I did not even look at your schematic on the assumption it's a hopeless mess filled with errors

 

[Warpspeed]

Joel, the buck inductor will reduce the output ripple amplitude to whatever limits you desire. But the input to a buck regulator is always going to be a step on/off pulsing current.

That is the usual reason for adopting the multi phase approach of having several buck regulators running in parallel out of phase. The peak input ripple will be lower, and of a higher frequency which is much easier to filter.
Far less total input filter capacitance and inductance will be required.

Input filtering of any buck regulator is going to present a serious problem to overcome where conducted emissions on the supply need to be taken into account.

Another topology for you to investigate is the coupled CUK converter. This has the unique property that both input and output ripple can be made to cancel.

Smoker is right, first try building a scaled down model, or one phase first. You will discover that the problems multiply exponentially with the current level. Four forty amp modules, no matter what topology you end up with, is a far more manageable approach.

 

[DHambley]

I'd go with 4 conventional peak-current-mode-control circuits to make all of the 4 converters share equal currents. (UC3842A for example, will work, although there are 100's of similar IC's). You don't need a digital controller. Make only one error ampiflier, based on the voltage loop. The output of this will feed the internal error amplifiers of the CMC ICs which you will set up as unity-gain followers. You need to also create 4 clocks to run all 4 converters out-of-phase. (App-notes for the IC's will show you how to use an external clock). Now, all of your converters will switch at the same peak current and the input filter will see the lowest ripple possible.

Allegro makes high-current Hall sensors with 120kHz BW (ACS156). If your switching Freq is < ~15kHz these might work. Otherwise, use current-sense transformers (and limit the duty cycle so that the CST's can reset).

Those are just a few of hundreds of tips I can come up with.

 

[joelg11]

I like this simplified approach hgldr. Turns out the controller I wanted to use has a min freq of 250kHz, which is higher than we'll be I believe. (looking at the 60-100k range).
The UC3842A datasheet is lacking in application detail, so I'll look around for an alternative.

Side question - Any complication to using the synchronous FET configuration with separate drivers? I assume I'd just route the PWM signal to the high side driver, and use an inverting buffer of sorts going to the low side driver. Assuming the timing worked out, I'd never have both on at the same time. Alternative would be using a synchrous driver like the LTC4449, haven't found one with the power ratings yet though...for reference I currently have the MIC4421A tabbed for use.

I'm learning a ton on this project already, thanks all for the comments.

 

[Warpspeed]

Just use FETs on the high side and flywheel diodes on the low side, that simplifies the whole deal.
As your output voltage is fairly high, diode voltage drop will not form a significant part of the total loss.

Going from 65v to 52v, the off time might be something like only 20% and at 150 amps dc, and with (say) one volt diode drop, that is only maybe 30 watts of diode conduction loss power loss out of 7.8kW of load power.

Just not worth trying to reduce that 30 watt conduction loss with another 150 amps worth of expensive FETS and drivers on the low side.

 

[joelg11]

Yeah warpspeed, after looking at the calcs there (even worst case duty cycle) that makes the most sense. Efficiency is the key for us over cost, but why is there so much out there that says synchronous FETs are the way to go? Is that just for low IV applications?

 

[Warpspeed]

Yup, if this was a 150 amp regulated supply for +5v or +3v, the situation would be completely different.

You could still use an active rectifier, but you will gain far more efficiency wise, by using more FETS on the high side switch than on the diode side, with your particular design requirements.

I would build up a low power prototype first, for maybe ten amps, and verify your design equations, and test that your control strategy and conducted emissions meets all your goals.

Then scale it up for forty amps. You will discover that physical layout, thermal design, and current sharing is just as important as the schematic and parts selection.

I would then combine four forty amp modules in parallel, rather than try to scale it up even further.

 

[joelg11]

Hgldr (or anyone),

Basic question. The datasheet to the UC3842B does show how to use an external clock synchronization, but I am having trouble conceptualizing putting 4 of these 90deg out of phase with each other. In the attached datasheet, Figs 21 and 22 are pertinent.

Does the internal oscillator of the CMC receive this clock input as logic input and only go high if the clk is high, etc.? Again, the phasing is a little beyond my reach right now.

Thanks for the help!

 

[joelg11]

here's the datasheet I didn't upload.

 

[Warpspeed]

The way to do it is to run a master clock at four times your required operating frequency.
Each of your 3842,s is then synchronized at one fourth the master clock frequency in ninety degree quadrature.

A two stage twisted ring (Johnson) counter could be used to divide your master clock by four, and the Q and not Q outputs provide four output phases in exact phase quadrature.

Small value capacitors could differentiate the edges, and provide the required narrow synchronizing spikes to firmly lock each 3842 in quadrature.

 

[DHambley]

The R/C colck input isn't logic level, it's about 1.2 to 2.8V. The circuit in fig 21 forces the R/C input to >2.8V which triggers the clock. The pulse width of this external clock only needs to be 100 or 200 ns wide.
What warpspeed wrote about pysical layout is important. Make an estimate for every parasitic inductance in the power path. Make the copper paths wide, no skinny, 20 mil wide inductors, er I mean traces. In your spice model for example, put 15 or 20 nH into your drain and source and watch the effect on the MOSFET power during turn on/off.

 

[joelg11]

Ok attached is my PWM schematic, which I believe is complete - working on a simulation now. I'd appreciate a verification that I've captured the advice I've received correctly.

Still ahead are dialing in the error amplifier ckt, and reading up on slope compensation for these UC3842s.

Thanks again!

 

[Warpspeed]

Have not looked at your schematic yet (no time right now).
But the buck topology does not require slope compensation for stability.

 

[joelg11]

There is just a lot of information out there, some conflicting I guess. The TI article I was going off of is

http://focus.ti.com/lit/an/slua101/slua101.pdf

where it states the case for bucks over 50% Duty cycle.