DC blocking design from 900MHz to 2.4GHz? 1

[bhalper]

Hello-

I'm looking for a simple method/circuit that provides DC blocking up to 2.4GHz with low insertion loss, 50ohm network. For this particular application, it needs to be redundant (ex. two capacitors in series) and rated to 125VDC. Spacing is also a requirement between terminals, which forces me to use a 1206 or larger package.

The two operating frequencies that I am concerned with are 902-928MHz and 2.4-2.483GHz.

How do I choose the capacitor values? Can it be done as simply as series caps?

Thanks in advance!

 

[VEBill]

DC Blocks are typically just series capacitors.

Here's a link to an example (Data sheet) and it includes a schematic:

http://www.minicircuits.com/pdfs/BLK-6+.pdf

Too bad it doesn't mention the capacitor value. But just choose a value that has very low series reactance, while minding the top end stray inductance.

Redundancy might be also provided by a parallel inductor in case the cap fails, it would short out the voltage.

 

[bhalper]

VE1BLL-

Understood that it is typically a series capacitor(s).

I've heard many people mention that they typically use 100pF as a value. I would need to make sure that the SRF is beyond my maximum operating frequency, correct?

 

[VEBill]

100pF at 902 MHz comes out as 1.76 ohms capacitive reactance. That's probably okay, but I'd use a larger value to reduce the reactance to an even more obviously trivial value.

Yes, you'd want to check and double-check for any stray resonances *as installed*. One option would be to sweep it with an analyzer.

 

[bhalper]

What are the downsides to increasing the capacitance to a larger value, say 1nF (or higher). Clearly the reactance decreases, but life is always a series of tradeoffs

 

[VEBill]

If all other variables were held constant, then the larger value capacitor might be physically larger and thus perhaps higher series inductance, or thinner dielectric and thus perhaps lower voltage. Of course, all other variables don't necessarily need to be held constant; the designer of the capacitor can optimize his or her design for each value.

If you're putting two in series, then you should lean towards a higher value to compensate.

Or use another topology, perhaps with a parallel inductor as backup.

 

[bhalper]

I really appreciate the help. I'm limited in the minimum size of the package/pads due to clearance requirements (1.3mm). Looks like I'm going to try and get the highest value in the 1206 package that has a SRF above 2.4GHz. Trying to work with AVX and ATC to see if they have anything they can offer since most RF packages end at 1210 (which does not meet my clearance).

 

[VEBill]

There's an old trick where you take advantage of the series resonant frequency.

With bypass capacitors (for example), one could estimate the installed lead length, and using charts and tables choose a capacitance value that would provide a series resonance at the desired frequency.

I actually used this trick once where I wanted to snub out a 40 MHz oscillation. So I determined the installed lead length and chose the capacitor value to give a series resonance at about 40 MHz. It was probably unnecessary (any old cap would have snubbed it), but I had a strong desire to nuke it.

Working with two frequency bands complicates this approach.

Good luck.

 

[bhalper]

Yeah, I had considered centering the SRF on the operating frequency of each band, but having two bands would mean I would have to populate the circuit with two different sets of capacitors. A more broadband approach is more manufacturable.

 

[Higgler]

In an old quad coupler design, we needed a dc block, we used just two overlapping printed transmission lines, insulated by dielectric gives a dc block, no capacitors needed. Once you print the layout and prove it, saves on components.

 

[bhalper]

Interesting Higgler. I'm not sure if I can afford a board spin to get that right, not to mention the simulation. What was your operating frequency?

 

[Higgler]

It was a bit higher than yours 5.8 ghz top end. Overlapped lines are capacitors.

 

[Higgler]

novel DC block printed on same layer, 1/4 wave length, dual lines

http://amsacta.unibo.it/364/1/Eug_6_2.pdf