DDR memory signal integrity simulation 1

[jamesnguyen]

Hi,
I am doing a design with DDR memory and I need to simulate the signal integrity of the PCB layout. Yes, I have never done SI check for the DDR memory before, so I don't know anything...

How do I find out the information such as voltage requirements (overshoot, undershoot, etc), timing requirements (rise time, fall time, etc), eye diagram requirements, etc?

Is there any tutorial out there on how to simulate the DDR SI under Hyperlynx?

Thank you so much!
James

 

[iop995]

Check this link. ftp://alag3.mfa.kfki.hu/PUB/JESD79C.pdf

 

[jamesnguyen]

Thank you so much! Is there any tutorial on how to simulate the DDR memory?

 

[zappedagain]

I believe Mentor Graphics has a few app notes about it. You might need to be on support for PADS to view it though.

Z