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DIgSILENT assistance

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ACTB

Electrical
Jul 15, 2003
2
Hi All,

Looking for someone who are familiar with the software to give me some guide on peforming some of the following tasks with DIgSILENT.

network impedance analysis, harmonic analysis, voltage flicker, power factor and effect of power factor capacitor.
Generally about power transmission and distribution engineering.

Thank you.

Best regards.
 
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Hello ACTB,

DigSilent can do all these things and more. Have you gone through the tutorial projects provided with the software?

It takes a significant amount of effort to become familar with the the software and unfortunately there is no quick path. My advice would be that you should attempt a small project (say with 4 buses) that has some complex models and about 40 hours later you will on top of it and find it is very powerfull and flexible.

I have found the DigSilent technical support to be very helpful, but if you narrow your question down to some specific issues and I may be able to assist

Regards,

AusPow
 
Hello AusPow

I am also using DigSilent (rookie) and what you said are so true. A question for you though. Do you perhapas have a small *.dz file that could assist me in modelling CT saturation. Awaitng your comments.
 
Hii AusPowEng,

Thanks for your advice. I did go thru' the tutorial. Yet, as i'm kind of fresh to the field(Power System Engineering) i might not clear on expressing the problem that i've faced.

I'm trying to study the effect of additional capacitor banks that add to a specific busbar. In the meantime, by switching them in steps (1,2,3 or so)how can i simulate or study on the effect that will cause any voltage flickering in procress. Did try to just add in the capacitor and run the load flow analysis with the software yet not sure that i'm on the right track.

Please advice. Thank you.
 
Hello Pentatek,

I haven't had to consider CT saturation in my DigSilent studies as yet, having only been a user for 12 months. I will take a look over the next week or so and will advise when I get something together.

Send me an email directly (pw.ycgi@bigpond.net.au) so I can return a '.dz' file to you.

Regards,

Peter
 
Hi ATCB,

What I would suggest is that you place switches or circuit breakers in front of each of your three stages of caps and then complete a load flow with those switches open. You then need to create timed events to bring in the capacitors and run an RMS transient study (whilst monitoring bus voltage in your system).

The load flow is necessary to determine intial conditions for the transient study.

If you have trouble, send me your .dz file & I'll see what I can do to help (pw.ycgi@bigpond.net.au).

Regards,

AusPowEng
(aka Peter)
 
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