Discharging Cap causing problem in biasing of power amplifier. 2

[jimmylovesni]

I have a single oscillator which is switching numerous matched mosfets arrays (n and p) in parallel. The circuit works as it was originally intended and is able to drive an ultrasound transducer at 1MHz. This circuit is attached (US_driver.jpg). A more detailed explanation is that a oscillator is driving a pin driver (7158) which in turns drives 4 other pin drivers. The pin drivers each drive 4 moset n/p pairs which are in parallel.

The problem. I want to start pulsing the 1Mhtz at 1Khz (pulsetimer.jpg provided), but am having problems where there is a delay it takes for the ultrasound to start pulsing where as the pulse timer appears to function as designed (attached n_channel_gate_pin4.jpg or p_channel_gate_pin2.jpg). In both files, the yellow trace is the 1KHz pulsing, the green shows that the 1MHz begins pulsing at the proper time. The pink trace is the output of the ultrasound driver with the transducer (load) disconnected. There is a lag it takes for the transducer to start pulsing. Im somewhat sure the problem is related to the blue traces (the gates) as they have a DC offset which diminishes in the area where the full power is delivered.

So there are .1uF caps that are supposed to block DC and allow only the 1Mhz pulse train though. But I think what is happening is that they are charging up when the 1Khtz pulse train is off. There is a certain amount of time it takes for them to discharge and reach steady state and thus regain proper biasing where there is no offset.

Any ideas on how to fix this? Even decreasing the C value will not completely fix it but just shorten the time constant a little.

thanks in advance.

n_channel_gate_pin4_blue.BMP

http://files.engineering.com/getfil...0baf5ab7da1&file=n_channel_gate_pin4_blue.BMP

p_channel_gate_pin4_blue_note_offset.BMP

http://files.engineering.com/getfil...file=p_channel_gate_pin4_blue_note_offset.BMP

US_driver.jpg

http://files.engineering.com/getfil...8cd-4988-afba-242996d4d6b4&file=US_driver.jpg

pulsetimer.jpg

http://files.engineering.com/getfil...7a-42bd-89c4-c4d57728fca2&file=pulsetimer.jpg

 

[VEBill]

What's "X" between the 7805 and the 3904? It looks like an xtal, but that makes no sense. Is that the oscillator that drives everything else?

The capacitor on the 7805 output is not connected.

Three of the 7350 outputs are not connected.

...

Can the pin drivers be connected directly to the 7350s?

 

[jimmylovesni]

there are resistors between the gates of the 7350 and pin driver.. If not, there ends up being some pretty large oscillations from impedance. they are generally pretty small in value, less than 10 ohms.

the x is just for a oscillator or crystal. It can be swopped out with function generator or other timing circuit.

I dont have pspice, just using pcb express tools to make the schematic, its pretty limited for parts and hard to see all the lines .. I did updates my schematic, thanks.

any ideas on the charging?

 

[VEBill]

(I only mentioned the typos because they're so minor that they might otherwise escape notice. It's best if they're killed on sight so they don't escape. )

The 4 ohm series resistors make sense. Seems like good practice.

The series 0.1 capacitors - I'm not so sure. I thought that the whole point of pin drivers was that they had enough drive that they could control (overcome) the gate capacitance (the gates of the IRF7350). It would seem that the series capacitors would delay bringing the gate voltages to the correct operating point.

But definitely get some second opinions (allow a day or so for more replies). There are better experts than I, that frequent this forum.

...

Is it normal with these sorts of ultrasonic transducer drivers that half the circuit is used to ground the drive side of the transducer (when the other side is already grounded)?

 

[jimmylovesni]

anyone else with thoughts?

thanks for your input VE1BLL. Ive now debating wiring up a prototype tomorrow (this is old project and already built pcbs on it) too see if this is salvagable

to answer your question, the half of the circuit (the n channel mosfet) can be connected to a negative voltage. Then the pulse waveform to the transducer would swing from -50 to + 50V rather than 0 to 50 V. Since we dont need the power, just using one supply is fine. To be practical, 40 volts on 1Mhtz vaporizes/ cavitates/ and levitates water about an 3/4 inch into the air.

 

[jimmylovesni]

was thinking about this a little more.. if the cap is removed, then there will be close to 50 volts on the output of the pin driver.

gotta be a way to do this.

 

[VEBill]

Put the transducer between the supply (+50) and the FET ("open collector" concept). Then you can drive the FET's gate with anything.

I built an alarm using that same approach: +12 volts DC, through a huge horn speaker, then the FET, then to ground (PS return). Tickled the gate with a noise maker and the huge horn speaker makes a very loud noise.

 

[IRstuff]

Amusing that neither of the two people responding are listed as EE.

I find your 0.1 uF and 820 ohm resistor structure very odd. Have you not considered it odd that it takes nearly 100 us to fully activate the transducers and that your capacitor and resistor have a 82 us time constant?

It seems to me that you've gone out of your way to turn transistors that switch off in ~30 ns into devicea that switch off in the tens of microseconds. You're trying to drive a 1 us period signal, so nothing in your circuit should have time constants more than about 20 ns, particularly if you want halfway sharp transitions.

As an aside, in the future, your p-ch devices ought to be physically above your n-ch devices on the schematic. Seeing a p-ch device at the bottom of a push-pull leads to momentary confusion and wasted time verifying that you've placed the positive supply below ground. These are conventions that allow engineers to read schematics without confusion. This is further complicated by the anti-convention of puttingthe p-ch source below its drain. Again, convention, and again, allows engineers to read the schematic with clarity. Likewise, one expects the two drains to be physically close to each other.

TTFN

FAQ731-376
Chinese prisoner wins Nobel Peace Prize

 

[jimmylovesni]

I appreciate your time, but saying the RC is funny is not really helping as it is something I myself indicated as being in question. Its how to get rid of the time constant, as in 0 dealy, that was interested in.

VE1Bll- thanks for your efforts again. Will try this next week.

 

[hacksaw]

try a resistor from pin 7 of the driver to ground

 

[Henneshoe]

The output is always enabled on the 7158 so the gate driver is pulled to ground. When the 1mhz pulse is off, the gate of the n-fet floats to 0V and the p-fet floats to 50V. Therefore, there is 0V across the n-fet gate capacitor and 50V across the p-fet capacitor. Once the first positive 1mhz pulse hits approx. 10V is added to each gate. Therefore, the n-fet gate is at 10V and the p-fet gate is at 60V. Once the 1mhz pulse goes negative, the n-fet will return to 0V and the p-fet returns to 50V. Through this cycle the P-fet never turns on. After a while, the inital DC bias is decayed and the p-fet gate oscillates between 55V and 45V, while the n-fet oscillates between 5 and -5V.

In order to remedy this, I suggest connecting your 1khz waveform to the OE pin on the 7158 drivers. This will cause the gate drivers to tri-state when the 1khz is off. Additionally, you should add resistors to 10V and ground to set the bias at 5V when the gate drivers are tri-stated.

 

[jimmylovesni]

henneshoe - wow! its working!! I just wired the 1Khz to OE. Im not 100% sure about the tristate though, I do have a voltage divider of 5V, via two 10ks, on OE, is that correct?

somehow clicking on "thanks" and giving you the little star somehow downplays my appreciation.
Jim

 

[jimmylovesni]

here is the scope shot of it working.. its just a protoboard circuit with one mosfet and pin driver, but none the less, shows its fixed.

http://files.engineering.com/getfil...-29e5-43ec-a251-950902e4a8c3&file=TEK0000.BMP

 

[Henneshoe]

No problem, glad to help. I hope this is a good explanation of why you should add a voltage divider to the output pin of the pin driver.

When the OE pin is pulled low is causes the output of the pin driver to tri-state. This means the output has a high impedance and isn't trying to pull the voltage high or low. At this time the voltage at the output of the pin driver is set by a voltage divider of the 50V supply with the 820 ohm resistors and 0.1uf capacitors attached to the gates of your fets. Therefore, with everything else being equal the voltage at the output of the pin driver should be 25V when the OE pin is low. The problem is the pin driver does not want the voltage at the output pin to to be greater than 10V because it would be outside of the acceptable range of the part. So in your circuit you have the pin driver fighting against the capacitors and resistors in the gate circuit to set the voltage at the output pin and the outcome may vary depending on part tolerances. (In your circuit it ends up at 10V.)

If you put a voltage divider on the output pin of the pin driver then you should see the voltage float to 5V when OE is low, and everything will stay within the part ratings.

The voltage divider is not absolutely necessary, but it is safer.

 

[jimmylovesni]

awesome, thanks!