I want to use 2 buffers each with a 6ns max. tpd
on a data line that changes at a 160MHz rate.
It's clear that the 2 buffers will add a 12ns delay
but does their tpd also limit the line data rate?
I have found that with certain logic families there can be a problem when the pulse width of the data is similar to the tpd. Under these conditions it can be difficult to guarantee that all devices will always switch properly. I would say your 160MHz is getting close (6.25ns) and especially if the data mark-space ratio is worse than 50 percent the pulse width could be 3ns or so. Use a faster type logic device!
It may depend on the reason for the delay. If the delay is the result of the rise time of the circuit, then the delay may smear the leading edge of the signal. With high frequency signals the smearing may be so bad as to make the signal unusable or undependable.
Signal smearing limits the length of fibre optic lines. You may have a similar effect related to the delay of the device. There may be a finite time required for the signal pulses to stabilize in the internal circuits.
Bill
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"Why not the best?"
Jimmy Carter
Quote from Waross: There may be a finite time required for the signal pulses to stabilize in the internal circuits.
This is very much the case I was referring to. Even when rise times are not a factor, as the pulse width reduces to less than or equal to the tpd of the device, the output pulse starts to become shortened in width compared to the input pulse until ultimately the device will stop switching reliably. The propagation delay tpd is realiable only for input pulses much greater than tpd. It's not unreasonable that a minimum amount of pulse energy is needed to 'fire up' the device stages and propagate the full pulse width through to the output.