Fetch/Execute Cycle 1

[Gurl1982]

Hi there,
I hope you can help, i wish to understand the data paths of the fetch-decode-execute cycle, i understand what the fetch/execute cycle does but are unabout to understand the steps in which the data flows.
Regards

 

[MMAshwin]

Hi,

What happens with the busses regarding the fetch and execute cycle very much depends upon the instruction being fetched. However at the begining the fetch cycle is pretty much the same for ny instruction.

1. The Program Counter(PC)in the CPU is passed to an Address Register and decoded to point to a physical point in memory.
2.The address is placed on the address bus and under the control of the Control Bus (read/write etc) the RAM 'puts' the data on the DATA BUS
3. The CPU reads the data stores it in an instruction register and decodes it into an instruction. This instruction will be spilt into 'microprograms' which tell the CPU what to do.

It is at this point where it depends on the instruction being fetched.

If the instruction was a single fetch instruction eg. NOP then the CPU executes the instruction, increments the PC and repeats the process.

If the instruction was a multiple fetch such as loading a register with the contents of an absolute address then there will be another fetch cycle. This will continue until all the parts for the instruction have been fetched, only then will it be executed.

What the CPU does after it executes the instruction again depends upon the instruction. Normally the PC increments and the next instruction is fetched. However if the previous instruction was a Branch or Jump then the PC will change accordingly.

Things are made complicated by Cache. If the instructions or data being fetched is regular it may well be stored on th CPU or L2 cache and so the fetch execute cycle may vary.

Any help ?, yes no let me know.

Regards

 

[Gurl1982]

the information u gave for good ty,
only i have a diagram that i don't understand, the main components r:
Main Storage

AUL
accumulater

Control Unit
program counter
current instruction register

memory buffer register
memory address register

sorry for pointing out all the parts only it's new to me and i don't know any other names for them

i wish to know the data flow if u can help i would be very greatful

Regards

 

[Gurl1982]

Hi there,
Laffalot or anyway with the knowledge please if u have any information on how the accumulator comes into the Fetch/execute cycle then please tell me, i know that it's inside the AUL and i know this carries out arithmetic operations, only all the sequenses i have found don't go through the AUL or even talk about the accumulater.

Please help if u call

Regards

 

[melone]

Could it be the ALU (Arithmetic Logic Unit)? If so, the ALU is used as a passthru stage to load registers in a 2 bus architecture system. When data is retrieved from memory, it must get placed on the register inputs. To accomplish this, the data must pass thru the ALU without being operated on and enter into the registers.

I apologize if I am not explaining this well. I will dig up some old papers that I did in college (I designed a 64-bit general purpose microprocessor with DSP capabilites using a standard 2 bus architecture microprocessor as a template) I will also look through some of my old textbooks and recommend something.

Good Luck!

 

[Gurl1982]

Hi there Melone,
Thank you for ur info.

Regards