frecuency stability(PPM) in a PLL

[davicente]

Hello, my name is David.I`d like to know if the frecuency stability of the output signal in a PLL is the same as in the clock reference used in the loop.I mean, if the reference clock is 4 PPM, and the PLL has a multilplicative factor x15 to obtain a 300 MHZ output signal, has this output signal also a frecuency stablity of 4PPM?does the PLL only make the phase noise of the output signal get worse?
I`ll be deligthed to know any link to application notes or articles related with this toipic.
Tanks in advance

 

[nbucska]

No, the PLL output can be more stable than the input.
There is a lot of data articles, etc. search e.g.
<

http://www.dogpile.com>

<nbucska@pcperipherals.com>

 

[davicente]

Thanks nbucska for your answer, but I didn't find a suitable article in the web, could you please be more specific about a weblink related with this topic?
thanks again.

 

[nbucska]

Hi David:
Search <

http://www.dogpile.com>

or <

http://www.google.com>

or
<

http://www.yahoo.com>

for PLL or phaselock.

or <

http://www.ti.com>

or <

http://www.onsemi.com>

or <

http://www.fairchildsemi.com>

appl.notes for PLL. Or

get from <

http://www.amazon.com>

Floyd Martin Gardner's
book about &quot;Phaselock techniques&quot;

===============OR===================
Do you have a specific problem?


<nbucska@pcperipherals.com>

 

[automatic2]

If your using IC devices, check with the manufacturer's app notes. Yes, output is directly dependant on reference stability.

 

[davicente]

Hi again nbucska,actually, I have an specific question:I'm working with a DDS which handles a 300 MHZ clock to generate a 120 MHZ output signal.The system obtains the 300 MHz clock from a 20 MHZ(4 PPM) reference through a PLL with a x15 multiplication factor.I know that the output signal from a DDS maintains the frecuency stability of the system clock (300 MHZ in this case), so the question is calculating the frecuency stability in PPM of the 300 MHZ clock , knowing that the reference for the PLL is a 20 MHz reference with 20 PPM.This is my real problem.
I hope this could help you to better understand my problem.
Thanks for your former answer, by the moment I'll try with last links you told me.

AREVALO

 

[nbucska]

The basic of the PLL: The frequency is controlled by the
AVERAGE of the phase error. Averaging == low pass filtering.

The frequency stability of the clock is a two edges sworld:

It may increase the max. frequency usable but generates more
noise. <nbucska@pcperipherals.com>