full-bridge PFC

[treez]

Hello,
I am designing a full-bridge active power factor corrector for a 600W SMPS.

The circuit diagram is as follows:-

I cannot use a standard boost converter type of PFC as the power level is too great.

MOSFETs 1 & 4 come on together …and 2 & 3 are the other pair which come on together.

I am worried about what will happen at the instant that a pair of MOSFETs turn off. –especially when the MOSFETs are switching on a low duty cycle. –Since their will be an accumulation of magnetising field in the transformer core.

The way I see it is that at the instant of switch –off. The Primary voltage will “flip” and the anti-parallel diodes across the MOSFETs will come into conduction –conducting away the magnetising flux as current. back into the mains.

-This is giving me a problem , since I am not sure if the mains can handle this “backflow” of current into itself. –Do you think I should put a small amount of capacitance across the downstream side of the mains rectifier? –so that this “backflow” of current can go into this capacitor?

(-Alternately, do you think that by slightly “phasing” the switching of the four MOSFET’s that I could circumvent this problem of the magnetising current having nowhere to go at the switch-off instant?…….
…i.e. turn 1 ON, then turn 4 ON fractionally later….
…then turn 1 off , then 2 ON fractionally later.
….then 4 OFF then 3 ON fractionally later…….etc…etc…etc)

The ultimate output of this SMPS will be 24V.

The SMPS downstream of the PFC will have its oscillator switching on at the instant that the PFC controller’s oscillator would be switching off if it were on 50% duty. –This will provide a smoother output voltage ripple for the output of the PFC.

 

[ScottyUK]

I cannot use a standard boost converter type of PFC as the power level is too great.

What makes you think that? You should be able to use a boost type active PFC into the multi-kW region to provide about 400 - 450V DC on the link.



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If we learn from our mistakes I'm getting a great education!

 

[Madcow]

You AC bridge should stop it from going back to the
mains.
How do you plan to draw current when the ac is on the
lower part of the cycle? ie. 48 volts to 0 volts.
Is the full bridge going to buck and boost?
Like Scotty said a standard boost pfc can handle KWs.

 

[treez]

I have a well known SMPS book which states that boost onverters should only be used up to 150 Watts.

I believe its due to the single switch having to take all the input voltage and having to take higher peak currents because boost's don't have bipolar flux drive like you get in a half bridge/push-pull/full bridge.

Not being able to draw much current when in the low part of the cycle seems fine to me.......that's the beauty of it...the current draw is supposed to be more, the higher the input voltage...that way you get a fundamental current input wavefom that's more in-phase with the voltage input...the Power factor goes nearer to 1.

 

[treez]

Sorry to drag this on...but i can't understand why the full-bridge PFC as shown above is not a standard design for >500W SMPS's.

This kind of Full bridge PFC is very simple and cheap to make and i can't understand why so many people buy off-the-shelf expensive PFC's. Something like a dsPIC controller could easily be programmed to coordinate the switching of the four mosfets (or IGBTs of you prefer and are using low frequency switching)...with Leading edge blanking time easily configurable, Dead time easily configurable etc etc

After all, the output of this PFC is going to get regulated by a downstream regulator so the PFC doesn't need good transient response or low ripple or anything........so its simple to do.

...in fact, the two upper MOSFETs of this full-bridge PFC could be switched without the hassle of isolation transformers and simple opto-gate-drivers could readily be used for isolated gate drive.

Also, the job of the downstream converter is much easier as it just has to regulate a fairly low voltage (compared to the rectified mains) -since full-bridge PFC could easily produce say 35 to 60V DC on its output.

...In fact, supposing a regulated 24V was required, -well then the PFC could produce say 35 to 60V.

Also, the downstream regulator (after the PFC) could be a simple one switch buck converter! (since bucks are good to about 1KW).

Also the downstream SMPS would not need to isolate its input from its output (-as long as its input was below 48V). -This makes its task so much easier as isolated voltage feedback is not necessary......thus direct voltage feedback can be used which aids transient response dramatically. (as opposed to using opto-coupled feedback).

The above shown full-bridge PFC could also be switched at 10's of KHz and use IGBT's...which are more robust than MOSFETS, and can handle higher voltage spikes, and should last longer in off line applications.

Does any reader know why the Full-Bridge Active PFC (as shown in the diagram in the original post) is not a standard item for use in off-line SMPS's of a few 100's of Watts? -It seems to be a winner i thought.

 

[ScottyUK]

Possibly because that market at that power level is incredibly cost sensitive, and as the current regs don't require a single load to have a near-unity P/F or to produce low harmonic levels, why spend anything at all trying to improve on the behaviour?

I am too long out of the power electronics game to know where the current legislation sits - maybe someone with more recent involvement can comment.

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If we learn from our mistakes I'm getting a great education!

 

[DHambley]

treez,

A Buck-type conveter is not practical for PFC. In order to get PFC the average current into your FWB needs to be proportional to the voltage. At high voltage, the pulse-width will be narrow and this means that the current during the pulse must be very high to get the average prop'l to voltage. Another big problem is that, at some level of the sinewave input, the voltage times turns ratio will be lower than your 48v out and no current will be drawn by the FWB. PFC will be impossible below this voltage.

Have you performed a little bit of math on this circuit, ie. pulse with vs. average current vs. peak current, etc?
You'll start to see inherent problems with a FWB topology after you do this.

(last PFC I did was 3 phase, 9kW, 3kW per phase. It is a boost type. The author of the book you've got must be stating some old rule-of-thumb from 1978 or something)

 

[treez]

Hi, Thanks all for replying.

hgldr:-
"The author of the book you've got must be stating some old rule-of-thumb from 1978 or something"

...The book i quote from is Marty Brown's 'Power supply cookbook', first Ed, ~1997.

Also hgldr:-
"A Buck-type conveter is not practical for PFC"

....though I am not using the Buck for PFC. It is the H-Bridge FET converter which does the PFC....This H-bridge comes downstream of the Full-Wave diode bridge.

....Downstream of the H-bridge is the Buck....which has the (now easier) job of providing the regulated output voltage, which in this case, happens to be 24V.

I think i may have explained myself badly here....the H-bridge FET switching converter is controlled by a dsPIC which is programmed to switch diagonal pairs of FETs alternately with an equal duty cycle all the time.....the duty cycle and H-bridge transformer will be selected so as to never let the core saturate. Without having to calculate anything, it is evident that the supply current will end up being roughly proportional to the Input voltage. Since when the H-bridge transformer primary has highest voltage across it, its current will rise highest. (from V=Ldi/dt)

ScottyUK:-
"the current regs don't require a single load to have a near-unity P/F or to produce low harmonic levels"

....i thank you for this, though I am surprised and am certain that there will be stict EMC regs applicable to single load converters....and that the configuration i described will make it much easier to meet whatever EMC regs apply to it.

I hear you say that it's possibly not worth spending extra on my H-bridge PFC...but it won't be that expensive, and there will be significant savings in the overall converter because the design of the Switcher that's downstream of the H-bridge PFC will be much easier (due to the reasons in the 5th post down). Also, the ease of design will cut design time and save on development time.

Incidentally, at a recent job interview with a huge US company that gets vast(!) numbers of (~300-1000W) SMPS's designed (and assembled) in Malaysia, I was shown one of the SMPS PCB's. -You guessed it.... the first stage of these SMPS's was an Active Power Factor corrector (The interviewers pointed this out to me)......and it comprised four FETs.....I can't help but think that it was probably like the one i propose in my first post above.

 

[DHambley]

In order to get PFC by using I = V*T/L, some inductor will have to work in a quasi discontinuous mode.
Is that what you're planning?

 

[treez]

I am going to start out with just an equal duty cycle switching strategy for the FET bridge. If the on-time is the same throughout then average current will automatically "follow" the rectified input voltage.

Yes I am first thinking of doing it discontinuously, it appears easier for my first 'go'