GND plane vs. ESD protection choice

[Chancy99]

Hi -

I'm in the final stages of the Datalogger design for cars. I had originally wanted to include clamping diodes on all the analog inputs, using the PACDN017 smd array from CalMicro.

http://www.calmicro.com/products/data/pdf/pac_dn017.pdf

After much pushing and shoving in the PCB layout, there is room, finally. Unfortunately, it would only be on the bottom layer - simply no room on the top layer.

Given that all the other components are SMD, the GND plane below the analog section is nice and almost unbroken. Good for analog signals If I add in this ESD array on the bottom, it chops that GND plane up but good.

So the question is, which is more important for a vehicle application ? Nice smooth GND plane, or ESD clamping diodes for each input ?

Dean.

 

[melone]

No, they are supposed to get better.

 

[Chancy99]

Hah ! Maybe if the complete design pops into my head from the start, hardware, software, the works, so I can just work a weekend and build it.

If there's any learning to do, or any "Wouldn't it be cool if we could ... " it seems to grow a life of its own, extruding pseudopods of creeping featurism.

I will not, repeat, NOT, consider adding GPS mapping and auto-calibration for inputs until at least the Mk. II.

Dean.

 

[Chancy99]

Argh. OK, after much pushing and shoving and measuring, it looks like I'll go with the larger 8-cap arrays. They have a lower voltage rating (25V) but will handle spikes up to 300% higher for a few seconds.

http://www.digikey.com/scripts/us/dksus.dll?Detail?Ref=32989&Row=244318

Although either the 4-cap arrays with 50V ratings (again, 300% spike handling) or individual 100V or 250V 1206 caps would be better, I have to keep in mind that at the moment, this thing is to be built by hand.

Those 4-cap arrays cram 8 connectors along the sides of a 1206-sized piece (3.1mm x 1.6mm). That's just going to be too dang fiddley to try to solder. The 8-cap arrays is a bussed design, 8 connections with 2 end-GND connections, in a larger 5.1mm x 3.6mm package. Not much better, but here anything is better

Version II, if it ever gets designed/built, may be a production run. In which case I'll go with the tiniest bestest devices I can find. Pick-and-Place is a wonderful thing, but not when it's my fingers and eyes doing it ...

Dean.

 

[carnage]

I have seen sand grains bigger than the new surfacemount stuff.

 

[tpavlic]

Wow. There has been a lot posted here; I don't have a great deal of comments to make on the ESD stuff that hasn't been mentioned here . . . Something I do want to mention about breadboarding . . .

When I first started in analog circuit design, when I was building my first prototype an older engineer asked what I would be building it on. I pulled out a breadboard -- I planned to deadbug the SMT components onto the breadboard for testing. He started laughing. Breadboards were for digital engineers, I was told.

Ever since I've gotten rid of the breadboard and now do all my prototyping dead bug on bare copper. This provides for a nice solid ground plane. It makes for some really nice more realistic low-noise low-distortion designs which don't fall apart at high frequency (a great deal of the work I do is in high frequency filters). It's easy to place all of your bypass caps everywhere you'd want them with as tiny leads as possible, and it's very easy to layout your circuit so that each component is as close (or as far) to each other as possible. Plus, your prototypes are easy to save and store for further use and reference. Sure, this requires you to brush up on your soldering skills, but under a microscope anyone can be a master solderer.

I've also had colleagues build similar prototypes dead-bug right on the surface of the PCB of an existing product being modified. This also works really well (a lot better than dragging wires out to some noisy breadboard somewhere).

Just a thought or two.

 

[Chancy99]

tpavlic :

Thanks for the tips. I was planning on making a few small pcb's for testing. I did pspice up the analog section, and it appears to be doing exactly what was expected.

I used SwitcherCAD III from Linear Devices :

http://www.linear.com/software

These are the three variations that the circuit will provide - you can just paste these into single files and simulate them in SwitcherCAD. Plot V(inp), V(out) and I(R5).

Dean.

==========================
0-5V input maps to 0-5V output

Version 3
SHEET 1 892 692
WIRE 452 288 472 288
WIRE 436 292 412 292
WIRE 412 316 412 292
WIRE 412 292 392 292
WIRE 412 360 412 348
WIRE 444 296 444 348
WIRE 444 348 412 348
WIRE 412 348 412 336
WIRE 444 280 444 232
WIRE 472 288 472 252
WIRE 472 288 496 288
WIRE 472 252 436 252
WIRE 416 252 404 252
WIRE 424 212 288 212
WIRE 244 212 244 252
WIRE 244 348 280 348
WIRE 288 212 244 212
WIRE 436 284 404 284
WIRE 404 284 404 252
WIRE 404 252 348 252
WIRE 288 232 444 232
WIRE 444 232 444 212
WIRE 280 312 280 348
WIRE 280 348 312 348
WIRE 372 292 312 292
WIRE 312 292 280 292
WIRE 328 252 244 252
WIRE 244 252 244 348
WIRE 312 312 312 292
WIRE 312 328 312 348
WIRE 312 348 412 348
WIRE 544 288 544 348
WIRE 544 348 444 348
WIRE 532 288 544 288
WIRE 496 288 512 288
FLAG 412 360 GND
FLAG 496 288 OUT
FLAG 312 292 INP
SYMBOL voltage 448 212 R90
WINDOW 0 -8 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL voltage 288 236 R180
WINDOW 0 6 26 Left 0
WINDOW 3 6 4 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL Opamps\LT1367 444 272 R0
WINDOW 0 4 8 Left 0
WINDOW 3 4 24 Left 0
SYMATTR InstName U1
SYMATTR Value LT1367
SYMATTR Value2 LT1367
SYMATTR SpiceModel LTC.lib
SYMBOL res 440 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R1
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 396 288 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R3
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 416 340 R180
WINDOW 0 9 19 Left 0
WINDOW 3 9 10 Left 0
SYMATTR InstName R4
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 508 292 R270
WINDOW 0 8 14 Left 0
WINDOW 3 0 14 Right 0
SYMATTR InstName R5
SYMATTR Value 1k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL voltage 280 288 R0
WINDOW 0 6 4 Left 0
WINDOW 3 6 26 Left 0
WINDOW 39 0 0 Left 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL res 352 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R2
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL cap 308 312 R0
WINDOW 0 6 2 Left 0
WINDOW 3 6 16 Left 0
SYMATTR InstName C1
SYMATTR Value 220pF
text 242 372 Left 0 !.dc V3 0 20 .1
text 244 160 Left 0 ;MegaLogger analog input section\nMaps 0-5V input to 0-5V output

==========================
0-14V input maps to 0-5V output

Version 3
SHEET 1 892 692
WIRE 436 292 412 292
WIRE 412 316 412 292
WIRE 412 292 396 292
WIRE 412 360 412 348
WIRE 444 296 444 348
WIRE 444 348 412 348
WIRE 412 348 412 336
WIRE 444 280 444 232
WIRE 472 288 472 252
WIRE 472 288 496 288
WIRE 472 252 432 252
WIRE 412 252 404 252
WIRE 424 212 288 212
WIRE 244 212 244 348
WIRE 244 348 268 348
WIRE 288 212 244 212
WIRE 436 284 404 284
WIRE 404 284 404 252
WIRE 288 232 444 232
WIRE 444 232 444 212
WIRE 268 348 300 348
WIRE 376 292 312 292
WIRE 312 292 300 292
WIRE 452 288 472 288
WIRE 300 348 412 348
WIRE 544 348 444 348
WIRE 544 288 544 348
WIRE 496 288 508 288
WIRE 268 312 268 348
WIRE 300 312 300 292
WIRE 300 292 268 292
WIRE 300 328 300 348
WIRE 528 288 544 288
FLAG 412 360 GND
FLAG 496 288 OUT
FLAG 312 292 INP
SYMBOL voltage 448 212 R90
WINDOW 0 -8 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL voltage 288 236 R180
WINDOW 0 6 26 Left 0
WINDOW 3 6 4 Left 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL Opamps\LT1367 444 272 R0
WINDOW 0 4 8 Left 0
WINDOW 3 4 24 Left 0
SYMATTR InstName U1
SYMATTR Value LT1367
SYMATTR Value2 LT1367
SYMATTR SpiceModel LTC.lib
SYMBOL res 436 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R1
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 400 288 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R3
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 416 340 R180
WINDOW 0 9 19 Left 0
WINDOW 3 9 10 Left 0
SYMATTR InstName R4
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 504 292 R270
WINDOW 0 8 14 Left 0
WINDOW 3 0 14 Right 0
SYMATTR InstName R5
SYMATTR Value 1k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL voltage 268 288 R0
WINDOW 0 6 4 Left 0
WINDOW 3 6 26 Left 0
WINDOW 39 0 0 Left 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL cap 296 312 R0
WINDOW 0 6 2 Left 0
WINDOW 3 6 16 Left 0
SYMATTR InstName C1
SYMATTR Value 220pF
text 242 372 Left 0 !.dc V3 0 20 .1
text 244 162 Left 0 ;MegaLogger analog input section\nMaps 0-14V input to 0-5V output

==========================
9-14V input maps to 0-5V output

Version 3
SHEET 1 892 692
WIRE 452 288 472 288
WIRE 436 292 412 292
WIRE 412 316 412 292
WIRE 412 292 396 292
WIRE 412 360 412 348
WIRE 444 296 444 348
WIRE 444 348 412 348
WIRE 412 348 412 336
WIRE 444 280 444 232
WIRE 472 288 472 252
WIRE 472 288 496 288
WIRE 472 252 436 252
WIRE 416 252 404 252
WIRE 424 212 288 212
WIRE 244 212 244 348
WIRE 244 348 280 348
WIRE 288 212 244 212
WIRE 436 284 404 284
WIRE 404 284 404 252
WIRE 404 252 348 252
WIRE 528 288 548 288
WIRE 288 232 304 232
WIRE 444 232 444 212
WIRE 280 312 280 348
WIRE 280 348 308 348
WIRE 376 292 312 292
WIRE 312 292 308 292
WIRE 328 252 304 252
WIRE 304 252 304 232
WIRE 304 232 444 232
WIRE 308 312 308 292
WIRE 308 292 280 292
WIRE 308 328 308 348
WIRE 308 348 412 348
WIRE 548 288 548 348
WIRE 548 348 444 348
WIRE 496 288 508 288
FLAG 412 360 GND
FLAG 496 288 OUT
FLAG 312 292 INP
SYMBOL voltage 448 212 R90
WINDOW 0 -8 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL voltage 288 236 R180
WINDOW 0 6 26 Left 0
WINDOW 3 6 4 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL Opamps\LT1367 444 272 R0
WINDOW 0 4 8 Left 0
WINDOW 3 4 24 Left 0
SYMATTR InstName U1
SYMATTR Value LT1367
SYMATTR Value2 LT1367
SYMATTR SpiceModel LTC.lib
SYMBOL res 440 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R1
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 400 288 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R3
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 416 340 R180
WINDOW 0 9 19 Left 0
WINDOW 3 9 10 Left 0
SYMATTR InstName R4
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 504 292 R270
WINDOW 0 8 14 Left 0
WINDOW 3 0 14 Right 0
SYMATTR InstName R5
SYMATTR Value 1k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL voltage 280 288 R0
WINDOW 0 6 4 Left 0
WINDOW 3 6 26 Left 0
WINDOW 39 0 0 Left 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL res 352 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R2
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL cap 304 312 R0
WINDOW 0 6 2 Left 0
WINDOW 3 6 16 Left 0
SYMATTR InstName C1
SYMATTR Value 220pF
text 242 372 Left 0 !.dc V3 0 20 .1
text 244 168 Left 0 ;MegaLogger analog input section\nMaps 9-14V input to 0-5V output
==========================