How to improve SDRAM clock signal?

[jamesnguyen]

Hi,

The SCLK of the SDR SDRAM on my layout looks like a sine wave! Its rise and fall times are so slow that there is not enough time for the required high or low timing.

There is only one SDRAM chip on the design. The clock line length is about 3 inches. I already use maximum drive strength but it's still not enough. The clock runs at 133MHz.

What else can I do?
Regards,
James

 

[IRstuff]

Use a better oscilloscope probe, perhaps? Is the circuit actually working?

TTFN

FAQ731-376
Chinese prisoner wins Nobel Peace Prize

 

[MacGyverS2000]

You have to be loading that line pretty heavily to turn it into a sine wave... no idea about what equipment you're working with, but IR has the likely culprit.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[IRstuff]

My answer wasn't quite as complete as Dan's. Your oscilloscope itself, may be too sloooooooow. You need on the order of 1GHz bandwidth to see a decent square wave at 133 MHz.

TTFN

FAQ731-376
Chinese prisoner wins Nobel Peace Prize

 

[jamesnguyen]

I use a Tek 750MHz FET scope probe with 2pF loading. Is it good enough?

James

 

[IRstuff]

I don't know; what are the specs of the driver?

750MHz is just barely 5x the fundamental. Even a perfect square wave is going to be rounded off with that frequency response. Don't forget that stated bandwidths are usually 3dB, which means that you're only getting 50% response at that frequency, so your 5th harmonic is reduced by 50%.

Again, is your circuit working at all?

TTFN

FAQ731-376
Chinese prisoner wins Nobel Peace Prize

 

[jamesnguyen]

The circuit works on about 80% of the units. I will try with 1GHz probe next

 

[MacGyverS2000]

Can you post that portion of your circuit? Just include the chip numbers and any circuits connected to the clock line only, please...

Dan - Owner

http://www.Hi-TecDesigns.com

 

[itsmoked]

What scope are you using?

Keith Cress
kcress -

http://www.flaminsystems.com