Need some confirmation re: 74595 2

[itsmoked]

Hello folks.
I have to serially string together three of these really nifty 74xx595 serial/parallel shift registers.

Here's the data sheet:

http://www.sparkfun.com/datasheets/IC/SN74HC595.pdf

A fellow engineer warned me that if I do that I could be losing the 8th bit on each chip. It was something about the serial output bit being the same as the last bit register, so, the first bit on the next '595 would have to be the same. Apparently he had to hack a board to fix this once upon-a-time, though he speculated that he was following the serial output with a display driver chip not another 595.

I'm not seeing it... I think I won't lose the last bits of each shift register. What do you know about it?

In a related question why are they calling this serial output QH[red]'[/red] ?? That sounds like it would be inverted but the two bubbles in that output chain should cancel to give a non inverted output. What am I missing in this "[red]'[/red]" nomenclature? Is that just meaning "next in time" and not inversion?

Keith Cress
kcress -

http://www.flaminsystems.com

 

[MikeHalloran]

It appears that QH' leads QH by RCLK,

and QH' is intended to feed into the SER input of the next chip in the chain,

as shown on page 2 here:

http://www.parallax.com/dl/docs/books/sw/exp/sw23b.pdf

( My friend Richard found it intuitive, but I have never understood TI's 'new' <since 20 years ago> logic symbolism. )




Mike Halloran
Pembroke Pines, FL, USA

 

[IRstuff]

It's NOT QH inverted, it's QHprime, i.e., another copy of what will be QH. Note that the parallel registers are one clock behind, so the serial out has to be taken from the output of the shift register, and not the parallel register to concatenate the registers correctly.

I agree that you get a full 8 bits. You'll need to stare at the timing diagram a bit. It's unfortunate that they didn't show an example of the QA SR output, which would make it clear why QH' is needed. The falling edge of QH' occurs AFTER the corresponding rising edge of SRCLK, so SRCLK clocks QH' into QI on that edge.

Your coworker must have spazzed the design and used QH instead of QH' as the input to the next register, thinking incorrectly that QH' was an inversion and therefore not usable. Since QH goes high a half cycle after QH', it will violate the setup time for the next bit, so he used QG as the last bit to compensate for the his error, losing one bit. I'm vaguely thinking that the SR registers actually have a one-half clock cycle setup time, i.e., valid data must be present on the fall edge of SRCLK, which is why QH', which is one-half clock ahead of QH, is needed to drive the next shift register.

TTFN
faq731-376

 

[itsmoked]

Thanks Mike for that "picture". I looked around and never found one.

IR; I bet you nailed it. The guy is the type to use the QH instead of prime.. That would totally explain it. "Prime" makes sense too. Right out of Complex Math.

I also agree with your rational. Thanks.

Onward and upward!

Keith Cress
kcress -

http://www.flaminsystems.com