Odd results in Arc flash using Etap 1

[majesus]

I notice in Etap if you have very small impedance between buses, you will get two very different answers for an Arc Flash calculation using IEEE 1584 Method

I have uploaded a photo of my SLD here for illustration purposes:

http://i48.photobucket.com/albums/f223/majesus/ETAPARCRESULT.jpg

I have the Main PDC located at the top and there is a secondary PDC (QMQB) about 10ft on the opposite side of the electrical room. Etap won't let you directly connect bus bars together so for initial simulation purposes, I just put a very small impedance (Z2) in between them with a value of 0.001 ohms for R,X,Y. This small value should be insignificant, and the two bus bars should be technically at the same fault. As shown, the short circuit was calculated to be 30kA on both bus bars. However, on the bottom bus I get an arc current of 24kA and an energy level of 11.99cal/cm2. But on the top bus bar, it blows up. The arc current is 24kA, but the energy is 8421 cal/cm2. Can anyone give me a suggestion as why? Is this an Etap algorithm problem? Maybe it is an issue with convergence?


I can fix the problem by putting a more realistic value for Z2.

 

[majesus]

I'm sorry, I made an error, I meant to say Z2 should be located above the top bus. If it is not there (0 ohms) the top bus blows up.


If Z2 is inserted at 0.001ohms, it works:

http://s48.photobucket.com/albums/f223/majesus/?action=view&current=ETAPARCRESULT.jpg

 

[majesus]

Grr, it posted the same link

This one:
(z2 = 0.001ohm)

http://s48.photobucket.com/albums/f223/majesus/?action=view&current=ETAPARCRESULT2.jpg

 

[jghrist]

It probably has to do with the clearing time for T1. With zero impedance, the clearing time must be high for T1, but the breaker between the top and bottom buses clears the bottom bus, limiting the arc energy.

 

[WDeanN]

I can't pull up the pics from the work computer, but I'm going to go with convergence. The 0 ohms is throwing ETAP for a loop. You may even look at the calculation method, and calculate from 3 or more buses away. I'd leave z2 in, maybe even reduce it further.

 

[Homerjs78]

It appears that the sub pdc has a trip device that is not protecting the main pdc. The two buses probably do not have the same trip device (and therefore trip time) used in the calculation. Are you able to send your one-line to their technical support for an explanation?

 

[majesus]

As always I appreciate you guys taking time to help me out.

I found out what the problem was, it actually was a simple configuration error.

Initially, I was thinking the bottom PDC was giving me the correct answer and the top was blowing up. In the end the problem was that Etap looks for an upstream Protection Device (PD) to calculate the fault clear time (FCT). The program's main configuration setting was set at a default of 3 bus levels above the fault level. For PDC 1, it was searching up and found the PRI XFMR fuse. The Fault clearing time was determined to be 83 seconds for this fuse.

For PDC 2, this fuse was 4 bus levels up. Since ETAP was configured to stop looking after three levels, the program will then set FCT to 0.1sec, hence giving the lower value on PDC 2.

What threw me off at first was that I though it may be a convergence problem. To validate my arguement I inserted a small impedance between PDC 1 and the Secondary side of XFMR. This creates an additional bus and now the fuse is four levels above PDC 1. ETAP didn't find it and default PDC1 FCT to 0.1s giving me the impression that PDC1 was the problem.