oscillator bank 1

[skelmonsta]

Hi all, I'm a software/DSP guy currently a bit over my head designing some hardware. I have a design in mind for my problem, but it's based on technology I would have used to do this twenty years ago. So I am writing in hopes of getting a "sanity check" on my solution.

Problem: build an 128-oscillator bank. Frequencies: 24000 Hz, 24093.75 Hz, 24187.5 Hz, ... 35906.25 Hz. Each oscillator must be on a different physical connection, for a capacitive sensor application. The spacing corresponds to a 1024-point FFT at 96kHz. Since they are all within one octave, the signals can be square waves (only the fundamental matters). Frequency accuracy needs to be 0.01% (+-4 Hz at 40kHz). Power needs I'm not too sure of yet, let's say a handful of mW at 5V for each oscillator.

This is a prototype that I will have to build. If it were a product, my solution would be: hire someone to design something, probably involving an ASIC...

Solution: The outputs are driven by TTL octal latches. A microprocessor (PIC) addresses the latches a byte at a time through some more TTL logic. The microcode updates a software counter for each oscillator and updates the latches when needed.

A vague solution, but hopefully precise enough to ask: is this at all the right technology to use? The correspondence of the frequencies to the bins of the FFT led me to think about solutions that would use this property to advantage. But it's hard to see how to do that given the need for separate outputs.

 

[Skogsgurra]

A really simple and very flexible solution would be to use a counter, 128 comparators set to their respective trig count and let them toggle their respective I/O pin and update to next trig count whenever the right count is met.

Now, what chip would you use for that?

IRstuff tipped me about the Parallax Propeller once. And I have used it a lot since that. It is fast, you can clock it at 100 MHz, which is good for a bit banger. It is a 32 bit chip. Which means that resolution or word length is seldom a problem. It has 32 I/O on each chip. So you don't need more than four chips for your 128 signals.

If it can do it? Fast enough? Yes, I guess so. And if one processor cannot handle it, there are eight of them on the chip. So each processor needs only handle four I/Os.

Power hungry? Yes, if around 50 mA is power hungry.

Expensive? Yes, if around 10 bucks is expensive.

Have a look at it - and smile.

Gunnar Englund

http://www.gke.org

--------------------------------------
100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...

 

[sreid]

A processor will not work because you have to make 128 decisions every, say, 2.5 nanoseconds whether to toggle a bit or not.

A hardware solution if yoy can relax the frequency accuracy a bit.

Start with a 12 bit counter running at 100 MHz (10 ns). With a comparator you short cycle the count to half the period you want. Then toggle another flip flop to get a square wave at the frequency you want.

So for example

2083 counts /2 = 24,004 Hz

2075 counts /2 = 24,096 Hz
.
.
.
1393 counts /2 = 35,893 Hz

1392 counts /2 = 35,919 Hz

Then for 128 13 bit counters you will need 16,000 plus flip flops. But in todays programmable logic devices, that's not a staggering number. You might have to use, say, 4 or 8 devices. A call to Altera, Actel or Lattice would confirm what you need.

These devices are pretty cheap and can be programmed onboard with a serial link from a PC. And the design software is free (and easy to use). And you really only need to design one counter, they are all the same except for the short cycle count number.

The frequency accuracy increases if the clock frequeny is increased but this increases the flip flop count. With multiple PLDs, one might be able to have slightly different clock frequencies (like 99, 100, 101, etc. MHz) to improve the likelyhood of finding a count that more closely matches the final frequency desired.

 

[Skogsgurra]

Yes, you are right.

The timing limits at 40 kHz are 1000000/40004 = 27.9975 us and 1000000/39996 = 25.0025 us. That is an interval being equal to 5 nanoseconds. Actually half of that since the waveform has to be toggled at 50 % also.

But, with 32 processors in four chips and a realaxed frequency spec, it would be possible. No need to do 128 decisions simultaneously.

Gunnar Englund

http://www.gke.org

--------------------------------------
100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...

 

[sreid]

Skogsgurra,

But doesn't it take some small number of lines of code to implement this simple function? And that would limit the rate at which one could toggle an output bit?

You and I are clearly on the same page except for the technology implemation.

 

[Skogsgurra]

Yes, it will take a couple of instructions in this processor. But there are processors with HSIO that usually can be set to toggle on timer contents. That is pure hardware and the number of available channels is usually limited. Often not more than six or eight. So, at least 16 chips would be needed.

I haven't checked new arrivals. There may be more competent ones among them.

Gunnar Englund

http://www.gke.org

--------------------------------------
100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...

 

[VEBill]

I guess the resultant peak phase error for any such proposed solution is easy to calculate. Estimate the period of the inner loop (lines of code & clock = heart beat) and then compare that to the period of the 35,906.25Hz (for worst case). That will tell you how early or late the transitions might be. If the code is tight enough, and the clock is high enough, then it might be acceptable.

 

[MacGyverS2000]

The 2.5ns time period you guys keep talking about is if you do not separate out the 40kHz base frequency and the add-on 93.75Hz signal. Separate the two, using the heterodyning idea, and your timing requirements drop significantly.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[itsmoked]

skelmonsta; Is there no other way to skin this cat?? This scheme does not sound very elegant. Often that means others are doing it some 'better' way.

Keith Cress
Flamin Systems, Inc.-

http://www.flaminsystems.com

 

[Skogsgurra]

That sounds elegant, Dan. You mean mixing the two and getting the resulting mix products spread out over the band? I guess that would produce the wanted signal components, but what about amplitudes? Do you not get a typical 1/n spectrum? Can schmitt triggers restore the square signals needed? No, I think. Can't quite see how that could work.


Gunnar Englund

http://www.gke.org

--------------------------------------
100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...

 

[VEBill]

The base frequency is of course 24,000 Hz (not 40,000 Hz). But there are advantages to not getting too close to zero. So the base frequency might be set to something like 20,000 Hz.

If you do simple mixing, then you end up with both plus and minus mixing products. By using a balanced mixer you can select which one you want and reduce the requirement for filtering. You need I & Q phases (90 degrees) to make it work. In a digital processor this might be easy. But I've never even thought about doing balanced modulators in digital as opposed to analog, so I dunno.

But the concept is one of those great 'break glass in case of emergency' ideas. If the other approaches aren't practical, then this one WILL make it work. But it might be something you would only do if absolutely required because of all the extra circuitry.

 

[benta]

I think you are missing the OP's requirement that all the frequencies must be physically separated, meaning 128 connections.

Benta.

 

[VEBill]

No. I think that we all noticed that.

My 2nd post in this thread mentioned "If...", but that was intended to compare and contrast (i.e. if). Another post half-way along mentioned 128 BNC output jacks.

 

[skelmonsta]

Let me first say a "wow" and "thanks" to the quantity and quality of discussion here. I was expecting a new idea or two to trickle in if I was lucky---as it is I have only just found time to keep up. This is a great forum.

0.01% seemed like a loose frequency requirement, but because of the short time slice required I see now it doesn't permit some of the simpler approaches.

A big, dumb loop still appeals to me a lot because I can simulate it and calculate the tradeoffs in software. But unless I'm mistaken, the access time needed is too fast to use a PROM directly. So the circuit gets complex, with fast RAM and whatever support that needs, and a boot state that loads the RAM from ROM. Sounds like I'm starting to build a computer, which means I could probably find an existing one to use for cheaper.

Calculating what one of the PIC systems, especially a parallel one, can do, is going to be harder. This is a promising solution which warrants a lot more research on my part, so thanks for those pointers.

I really want heterodyning to be useful, but I see some problems. One is that the base frequencies are not multiples of a fixed timer interval, they are linearly spaced frequencies in Hz which makes the intervals logarithmically related. So that's a bit tricky. The other is that with square waves you get the sums and differences of all the spectral components. I think you need to have sine waves for carriers if this is going to work.

Cascaded counters on programmable logic is a very cool solution. It has the nice advantage of being easily scalable once I get something working. Another advantage is that my prototype can be largely the same as my finished product. I have to research what it takes to get started with FPGAs, and what kind of circuitry I would need to support the chip and drive the outputs.

Itsmoked steps back a pace: "skelmonsta; Is there no other way to skin this cat?? This scheme does not sound very elegant. Often that means others are doing it some 'better' way." A reasonable suggestion since I've left out the elegant part of my solution. A commodity audio interface will be used to send the sum of all the carriers to a PC where they are decoded in software. So I get 128 channels of analog data to the computer for cheap. The frequencies of the FFT bins are also usable directly for capacitive sensing over short distances to a common antenna. So once I make my oscillator bank, it's both a sensor and multiplexer. (a floor wax *and* a dessert topping!)

 

[VEBill]

I don't completely understand the overall application, but I've a simple question for you to consider. If the ultimate destination is an FFT, could you accomplish the same thing with some white noise covering the required spectrum?

I guess this goes back to the 128 separate channels...

By the way, there are many modern data communications methods that rely on having 'a zillion' parallel carriers. ADSL, BPL (damn them), I think BlueTooth, and probably many more. It might be worth seeing how they create so many closely-spaced carriers. The USPTO might be able to help.

 

[sreid]

So, if I understand corectly, you would have to modulate some signal information on to all 128 carriers? Wouldn't an A/D conversion followed by a Time Division Multiplex be the more usual way to go?

 

[MacGyverS2000]

The $10 million question... what exactly is the application? Will there be one made or 1 million?

Dan - Owner

http://www.Hi-TecDesigns.com

 

[skelmonsta]

VE1BLL, thanks again- I did think of using FFT hardware, but my requirement for separate physical signals makes it useless unless there's some really profound hack I'm missing. Hardware FFTs work a lot like software ones-- there is a butterfly pattern of multiplications. For an IFFT, the input is separate channels in the frequency domain, the output is one combined channel in the time domain. I need separate channels in the time domain.

The application: imagine a carrier signal in the kHz applied to one antenna a couple of mm from a receiver antenna. The two form a capacitor, and so signal strength in the receiver is inversely proportional to the distance between the pair. I need to get a 2D "image" of the deformation of one surface with respect to a fixed one a couple of mm away into a computer. So, I make the fixed surface a plane antenna and put the carriers over it on the deformable surface. The sum of the carriers contains all of the position measurements as one audio signal that can be decoded on the computer.

Cost is definitely a factor. I would like this to be a sort of cottage industry project or a kit of which there might conceivably be at least hundreds. So, using these carriers to both do the measurement and modulate the data seems like an elegant solution.

 

[MacGyverS2000]

I don't even want to imagine what kind of mixing you're going to get between all of those signals... sidebands are going to look like hell!

Dan - Owner

http://www.Hi-TecDesigns.com

 

[VEBill]

Mixing products can be predicted if you know the linearity of all the steps in between. Audio equipment is usually pretty good in this regard.

Other concepts:

Just switch ONE signal between the 128 output antennas at a rate fast enough to track the (assumed to be slow) physical motion. Switching is easy. There are even 'binary search' tricks using banks of half, quarter, eighth, all the way down, instead of a linear one-by-one approach.

Or perhaps launch acoustic waves across the surface to modulate the distance so that a single parameter will reveal in time the 2-D position.

Or use an optical technique. Holography for example is excruciatingly sensitive. Or laser scanning which is very cost effective these days using cheap bar code hardware.

But perhaps this concept is new and worth trying.

 

[skelmonsta]

There is significant crosstalk, but calibrating for this is not a problem. I appreciate the point about sidebands, but my prototype has worked well so far---as long as I make sure there is enough headroom in the mixer for linearity with more carriers I should be OK.

Any oscillator bank solution will need to source a whole bunch of current when a lot of oscillators are positive simultaneously. This won't happen very often, but when it does, we would like the machine not to break. Roughly 1A total is my back-of-the-envelope result--- what would people add to an FPGA or PIC to do this? Are Darlington arrays appropriate here?

Thanks VE1BLL for all the other suggestions. I have investigated many of these technologies, and others have built some of them, but they tend to have bandwidth limitations. Switching might be part of the answer, but in general this requires synchronization with the FFT step. I was really hoping to keep all of the smarts in the computer.