PCB routing (clock lines and termination) help 1

[RobF]

Well I thought I did a decent job with my board layout/routing until the FCC test report came back *FAILED*. At least it was nice of them to put it in all capitals, made me feel better After reviewing the emissions report, it appeared a majority of the emissions were at every harmonic (even & odd) of the 75Mhz bus, in both vertical and horizontal planes (antenna polarity). These harmonics exceeded the allowed field strength of about 23db.

System specs:
*150Mhz processor with a 75Mhz address/data bus located on what we call a processor board with memory and other cpu-related peripherals.

*6 layer board in this order from top to bottom: (1)component/trace, (2)split power plane, (3)trace, (4)trace, (5)ground plane, (6)component/trace

*processor board plugs into a backplane board which could be conceptualized as a "motherboard." this board provides power and the circuitry for driving high current outputs. It also has 5 additional connectors (68pin) for expansion cards. The address bus and data bus are run to these connectors along with power, and some other misc i/o.

*all signals entering/leaving the processor board use bidirectional buffers located on the processor board.

*NO signals have any kind of termination on either board. The scope shows no reflections and aprox a 1V overshoot on a randomly sampled data line on the processor board.

*clock line is 75Mhz sine wave and is routed to all peripherals on the processor board, through the buffers, and to all expansion connectors on the backplane board, again, no termination.

Maybe I shouldn't have expected it to pass?:
As a saving grace (maybe), the enclosure is not shielded and neither are the cables entering/leaving as of the FCC test. Now I have added a spray on conductive paint exactly for shielding plastic enclosures and I have changed the cables to include a sheild (foil or braid over foil) with the drains tied to ground through a pin on the connector (not the best but I cannot switch to metal housing connectors as they're not available)

I'm now at the point where I'm going to build the next revision of the board. I was told to add a filter to every i/o line possible entering or leaving the box. I have chosen a ferrite and capacitor in a two-pole style low pass filter which will actually end up being a T filter when im done as seen here ...

http://www.specemc.com/hermetic.asp

Questions:
1. what is the best possible way to route the clock line to significantly lower my RF emissions from it.
2. Is my method for adding the T filter to every i/o before the external enclosure connectors sufficient?
3. Do I need to terminate any/all of my bus lines? Why or why not?

Any other suggestions?

And of course, thanks for taking your time to help me.

 

[VEBill]

"Any other suggestions?"

One sneaky (evil?, clever?) trick is to use a dithered clock to spread out the frequency domain peak(s) over a slightly wider bandwidth. Ref: EDN, May 11, 2006, page 61.

Also:

http://www.sigcon.com

General EMI advice: If you know about good antennas, just do the opposite.

 

[Comcokid]

Get and read High-Speed Digital Design - A Handbook of Black Magic, and the 2nd book High Speed Signal Propagation - Advanced Black Magic, both by Johnson/Graham. You may already have these.

Get a spectrum analyzer. Obtain some near field probes - such as ARA HFP-7410 or Com Power PS400 (do a Google). Optionally, make a sniffer as discussed in Conformity magazine Nov 2002, or thread247-81695. I seem to recall other threads discussing this, but was unable to locate them. Anyway - use a probe and analyzer to localize and get a general idea of where the most radiating places on the PCB are.

Buss lines conducting fast-edge signals are transmission lines. They can radiate if not terminated, or if they have impedance changes along their length. Antennas are similar structures. Buss lines made carefully and properly can carry GHz clock signals without radiating.

 

[jimkirk]

http://emcesd.com/

has all sorts of useful articles & tips.

 

[geekEE]

Is the clock really a 75MHz SINE wave? Clocks are typically square waves, which will have all kinds of nasty harmonics unless you limit the edge rise-fall time.

I highly agree with getting the Howard Johnson book. Excellent stuff there.

 

[RobF]

Thanks guys for all the suggestions so far. I'm going to read through all of this documentation online and maybe purchase a book. I've been reading the EDN designer's guide to EMC which has had some great info!! I am also anxious to try the inductor RF probe idea.

The clock is indeed a sine wave. I wasn't the one working on the processor board so I don't know much about it but it does sound weird and I will look into it further. All i can say is that its a sine wave on the scope heh

 

[IRstuff]

The fact that you have harmonics of the 75MHz says that somewhere on your board you have 75MHz square waves

TTFN

 

[RobF]

Turns out the scope i'm using is only 100Mhz and i'm sure you know the rest.

Apparently we dont own a >100Mhz scope (yet )

It'd be nice to be able to see the clock but i'm not sure how much I could disern.

 

[IRstuff]

What did you do to prevent emissions from the board in your design?

TTFN

 

[RobF]

We did a few simple things such as insuring the data bus was burried between two copper plane layers (vcc and gnd) along with the clock. Additionally we tried to keep bus lines as short as possible and away from analog and i/o lines. No one ever mentioned terminating the bus lines, bus impedance and/or impedance matching, or any other high speed routing techniques (altho we haven't had any problems with the bus yet just emissions). Emissions prevention isn't a well known topic around here (apparently).

I built a sniffer as recommended using a 1uH inductor (didn't have a 10uH) and the results were somewhat surprising. It seems the board connectors are the largest culprit. Yes, there are some parts of the board that are noisier than others (in the 75Mhz realm) but I saw a >14dB increase from the noisest section of the board to the connector that connects the two boards together. The only thing I can come up with is that this is caused by a lack of ground plane and/or shielding.

I dont think there's anything I can do about that. Even if i had a perfect board layout, the connectors would still be emitting the same energy which is probably what is causing us to fail. After seeing how much greater the emissions is from the connectors compared to the board, I'm starting to think the board layout isn't as bad as I originally thought.

Anyone have any ideas, is my hypothesis correct?

 

[VEBill]

The topic of board layout could be considered to include the assignment of pins on the PCB-mounted connectors. Often, alternating signal and return pins are assigned to keep the noise down.

 

[MikeHalloran]

Just a shielding suggestion, based on several expensive adventures with grand intentions:

Conductive paint doesn't work. Spray-on, brush-on, expensive, hideously expensive, egregiously expensive, they all ... don't work.

Sprayed-on conductive shielding, e.g. arc- sprayed metal, doesn't work.

Electroplated copper shielding on plastic doesn't work.

The problem is not that the stuff is not sufficiently conductive, but that you can't maintain a reliable ground all around its periphery, i.e., it can't be terminated.

Keep the plastic, but line it with nickel plated steel, with closely spaced grounding fingers along all seams, and no big holes. The few Apple desktops I've disassembled were pretty well made in this regard.

Beware the razor edges.



Mike Halloran
Pembroke Pines, FL, USA

 

[zappedagain]

" cables entering/leaving as of the FCC test"

Cables make great antennas. Did you ever see a consumer device with a clip-on choke on the power cord? That's why. I've seen more failures off the cables than off PCBs; I once saw an 11 dB improvement by adding a choke (onto the PCB). You may need to do the same thing.

Search "Ferrite Cores for Cables & Wiring, EMI" at Digi-Key and you'll find some inexpensive (but not very pretty) options.


Also, do you have bypass caps at every IC? The bypass caps make a nice small loop for the AC currents; without them you have a large loop that can radiate H-field. I've seen over a 3 dB improvement off better bypassing.

Kimmel & Gerke (

http://www.emiguru.com)

did a great write up in the 1990s in EDN about EMC/EMI issues. It is supposed to be back in print again; check their web-site.


Good luck,

 

[BobbyNewmark]

The references recommended above are good. Read them and become enlightened.

How many power/ground pins does the connector have? (The one between the processor board and the motherboard.) If you're sending a 75 MHz data bus across, you should have about one power/ground pin for every signals, and every power pin should be bypassed on both boards with its own SMT capacitor. The return pins (power/ground) should be evenly distributed across the connector. For good examples, see the pinouts for the PCI bus connector and DIMM memory modules.

The split power plane is also a worry. Every high-speed trace has matching return currents on the nearby planes. When a trace crosses a gap between two planes, the return current will be forced to follow a long path that acts like a loop antenna.

 

[Warpspeed]

Hmmm....

I would say that it is highly unlikely that the signal is being radiated direct from the circuit board itself. If all the clock and bus lines are buried between two solid copper planes, there should be negligible radiation. Make sure the two surrounding planes are liberaly stitched together with plenty of bypass capacitors spread over the whole area.

Those high speed signals may be leaking into other parts of the circuit which then enter or leave the board througn the external interface connections. It sounds to me as if it is the external wiring connected to the board rather than the board itself that is doing all the radiating.

Hire a spectrum analyzer and build a sniffer probe. While trying various things, it is sometimes difficult to know where you are heading. You will usually be able to see fairly strong signals from local TV and FM stations on the spectrum analyzer, and they make a handy reference signal level with which to assess progress. You know you need at least 23dB reduction, and the dB divisions on the spectrumm analyzer can be used to compare local radiation strength to the strength a particular TV station at a certain distance from the board. With a bit of imagination you can estimate how much certain improvements are able to give. It is all a bit Mickey Mouse, but I have done this myself succesfully several times in the past, and have usually just scraped through on a retest by a few dB.

 

[RobF]

I Haven't checked this in a while, sorry for the delay. I want to thank everyone for their comments and suggestions!!

On to the party...

MikeHalloran: I hope you're wrong but assume you have plenty of experience. I just sent off a box that had been sprayed and has sheilded cables. If we dont pass then we have two more alternatives in the works. One, I'm currently redesigning the mainboard with filters on all i/o lines (ferrite and cap in a T configuration). Secondly, I will be suggesting your nickle plated steel to my boss. I know i've seen this type of shielding somewhere I just can't put my finger on it. It sounds like a really great idea and I've put it on my list.

zappedagain: Yeah, up until a few years ago I always wondered why those were there. Now that I've been dealing with EMI issues a lot more lately, I know all to well why they're there. I should've got some ferrite cores and put them on our stock harness before I sent it out but I didn't even think about it. I wonder if these would help with an already shielded cable? As for bypass caps, every Vcc pin has one and I made sure. Some IC's have many VCC pins (processor, CPLD, etc) and each one has at least one cap of 0.1uF or 0.01uF. I actually have a copy of BOTH the first edition and the newest one on my desk. ITs very informative and I'm working my way through it learning TONS. Anyhow, maybe i'll get some chokes from digikey and send them to our test house to add to the cables.

BobbyNewmark: The connector has probably 3 or 4 power and matching grounds (have to check for sure when im at work tommorow morning). So do you mean every bus lines should have a vcc/gnd?? That would make my connector ENORMOUS!! I will look atht he PCI bus connector, thats a good idea. When i built the power planes, I made sure there wern't any gaps on it and that it filled around each connectors pins. I'm going to take another look at it to be sure.

Warpspeed: So you would add bypass caps that dont belong to any particular IC evenly spaced in a grid on the board (per se)? I definitely think we have some high-speed bleed over onto some of our I/O lines. This is why I'm working on adding a filter to all the I/O lines in and out of the board. I did build a sniffer probe and I can see the 75Mhz noise around the board but its not too much greater than the noise floor (of the noisy engineering dept if that means anything). Its when I get to the connector between the boards that the spike goes off the screen. You say "at a certain distance from the board," I assume you mean with the RF sniffer probe. When I was doing the sniffing i was pretty much right up against the board. I couldn't detect anything when i moved a few inches away because there was so much noise in the room. Should I be able to? Maybe I need to go somewhere quieter (RF wise)?

Thx again everyone and I'm going to go rack my brain (tommorow).

 

[MacGyverS2000]

For high-speed lines, you should have a ground line for each one once it hits a connector... not doing so is a sure-fire way to get coupling between lines. If the connector lines are of the correct length (think harmonics, too), you're going to get some great radiators out of them.

Also, do you have any bulk capacitance in there to supplement the 0.1uF? Something one the order of 4.7-10uF should be good, sprinkly those in amongst the 0.1uF, say 1 bulk cap for every few 0.1uF, maybe more near chips that have multiple Vcc/Vdd pairs (e.g., large processors). Bulks will provide "local supplies" for the smaller caps, helping to prevent some of the high-freq power draws from being pulled from across the board.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[kf6bbl]

Don't know if it's too late, but here are my suggestions on things to look into.

1)Termination - you mentioned there was none, and you have 1V overshoot on your data lines. That much overshoot means you have no control of your rise times, which is a major factor. Consider some series termination (damping) of each device on the bus. Each IC on the bus should be isolated from the bus through a resistor. They make tiny (0402, 0603, etc) 8x and 16x resistor networks for this. Start small (10 ohms) and go up as needed to get control of that overshoot. In reality what you are doing is impedance mating to the bus.

2)Backplane termination - Design an active or passive terminator card to plug in at the end of the bus on the backplane. Probably easier than redesigning the backplane.

Another thing to consider is your scope may be lying to you. If you are looking at 75MHz with a 100MHz scope, do some sanity checks like calibrating your probes if possible.

3)GND plane de-splitting - you didn't mention the integrity of the GND plane on layer 5, but it should be 100% copper, no splits, and watch for too many vias created unintended splits. Don't even split for analog vs. digital. I know some will fight me on that. This is probably what is really causing your problem. You can bury the bus under 15 layers of planes, but I am guessing that your GND plane is the one radiating signal out to the other traces and chassis, not the bus itself. At 75MHz, you GND plane has the equal and opposite 75MHz currents flowing through it. If it has to take a long path around a split plane, guess what? A loop antenna!

As an anecdote, I always wondered where they hid the antennas on fighter jets. Anything like that tends to get stripped off at Mach 2. Finally I found them hidden in plane sight (yes, a bad spelling pun). The metal skin of the aircraft has resonant slot, and the center of the slot is fed with the RF signal, ground to one side, signal to the other. Turns out a large flat piece of sheet metal makes a great antenna, all you need is a slot and a current traveling around the edges!

-Bill

-Bill
CE Designer Forum

http://www.cedesigner.com

 

[analoguealan]

Even with multilayer boards, it is good practice in order to assist in meeting EMC emissions to provide guard traces for all high frequency clocks. This effectively provides the clock trace with its own private return path, taking the clock noise current out of the ground plane. This assumes use of the top layer for fast signals and layer 2 is the ground (or more accuratley reference plane). Radiation is kept minimal by running the guard traces as close as possible with the clock signal trace, for minimal loop area. It also helps to,

Define and maintain a constant line impedance.
Reduce susceptibility to crosstalk with nearby board circuitry.
The guards are pinned to the ground plane at the source and destination points or as near as possible.
With modern CAD/PCB manufacture you shouild be able to use minimum trace widths of 5 mil and 5 mil separation.
Study EMC websites there is a lot of good stuff around.

Analogue Alan

 

[itsmoked]

Nice info analog.

Keith Cress
Flamin Systems, Inc.-

http://www.flaminsystems.com