Phase-Phase fault detection 1

[pavement]

Can any of yous guys offhand, suggest a solution to detect phase-phase faults on a Dd0 system, where the lowest fault current due to arcing resistance, no inductive contribution is lower than the actual load current at that point? Obviously you cant simply set the current pickup on a standard IDMT at this lowest prospective fault current as normal operating currents would set it off?!?! So basically im stumped what direction to go in.


Many thanks in advance for any input no matter how small.

 

[Mstrvb19]

Since the arcing fault is the only condition under which you will see phase to phase faults at or below your normal operating current (yes?), there are a couple of things you could do. First, some breaker manufacturers are producing breakers with arc-fault protection (optical). These devices trip when a flash is detected in the cubicle (or a remote cubicle if there is one). If you are looking at a situation where the potential flash is not in a cubicle, you could set up a phase balance relay system, since it is highly unlikely that an arcing fault occurs on more than two phases, and the third phase would be left supplying your load. I am unsure though, about how you would set up a system that is "contingency free". I am interested to see if anyone else has ideas on this.

 

[stevenal]

Negative sequence relaying is the ticket for line to line faults. If your loading is three phase you should normally see little or no negative sequence currents, and can this element can be set low without risk of tripping on load. Usually included with microprocessor multi-function relays.

 

[RalphChristie]

To add to stevenal's comment:

Have a look at the website of SEL. They have useful information regarding detecting faults with negative sequence currents.
Normal loaded systems (balanced) just have positive sequence currents. Phase-phase faults consist out of positive and negative sequence currents. Because there is no negative sequence currents in a balanced system, you can set the setting normally at 1% or 2% of the possitive sequence current setting.

http://www.selinc.com

Regards

Ralph