Scrambled clock / data.... 1

[melone]

Could someone please explain that basic concepts of scrambled clock / data signals? I am currently working on EMC reductions on PCB's and have heard that scrambling the clock can reduce emissions by 24dB! Also, how much jitter can I expect with a scrambled clock signal?

Thanks in advance for all of your help!

 

[zubairkhan]

Can the application of the exercise be highlighted. Only then some input can be provided.

 

[melone]

Due to the proprietary nature of this project, detailed information cannot be provided, but a BASIC scenario can be given. Let's say that I have a microprocessor that takes a crystal input and generates a clock signal in the 5-10MHz range. Then this clock is run to several IC's that require a clocking signal. These IC's are either output drivers (low-side) or communication controllers. Unfortunately, I cannot give any more info. If this isn't enough info, please point me in the right direction in where I can do the research. I have tried a google search and came up with nothing.

The purpose of this project is to try and reduce the RF emmisions on this PCB by reducing the RF harmonics created by having a standard clock signal run over a fairly long area of a PCB (4-6 inches). Hopefully, by scrambling the clock, the harmonics will be significantly lowered (approx. 24dB).

Thanks in advance for any help!

 

[nbucska]

A constant energy of a frequency + harmonics is concentrated in narrow bands, the FM spreads the energy around wider bands resulting in lower energy density.
<nbucska@pcperipherals.com>

 

[melone]

Actually, this is differenct than simply FM modulating the clock. Scrambling the clock should produce a pseudo-random sequence thus signifacantly spreading the energy over a large spectral range. Therefore, I should have a scrambler circuit after the clock generator, and descrambling circuits at each recieving node.

On the other hand, FM modulating the clock after the source by a fairly high frequency can negate the need for the demodulation at each recieving node. Unfortunately, this solution does not provide enough sprectral density expansion. Therefore, to achieve acceptable peak reduction, I would need to modulate the clock with a low frequency signal. Thus, a demodulation circuit is needed at each node.

Therefore, if I must have a descrambling circuit at each node, I would like to try and minimize the peak spectral denisity. A truly random sequence of 0's and 1's should produce the smallest peak denisities. Unfortunately, a truly random sequence cannot be used as a clock, but a pseudo-random sequence can.

Hopefully I have not insulted anyone's intellegence. I just wanted to explain why I am going down this path.

Thanks for everyone's help!

 

[sfi]

Instead of having one high speed clock + line, hows about using two clocks and a low frequency line which resyncs the two clocks.

 

[melone]

SFI, Could you point to an example of how something like that is setup? It might work, but I still have some reservations. Instead of having 1 clock oscillating at 5-10 MHz, are you suggesting that I run 2 clocks at a lower frequency and resynchronize them at each node? If that is what you are suggesting, then I have doubled the possibility for RF emmisions. I would agree that the sprectal density will change by utilizing the slower clocks, but now there are two antenneas radiating instead of one. Perhaps I am misunderstanding what you are saying (it wouldn't be the first time I got something wrong!).

Thanks again!!!

 

[MMAshwin]

Hi,

Just a thought.

Why not have a much higher clock frequency than you actually require. Of course this radiates more (but over a shorter distance ? maybe).

Anyway this is your master clock. At the chips that actually require the clocking signal, you delay and reduce the clock speed. E.g. Divide the Clock by N.
Providing all parts of the PCB requiring a clock are divided by the same amount the data will be syncronized.

Now lets say you change the divide by N to divide by N+X through control lines to the dividing ICs. Your clock frequency to the ICs changes but it does this throughout the circuit so it still should be sync'd.

How often you change it, is up to you. Get a fast enough microcontroller, perhaps, and you could change it every 8 bits.

Any radiated signal data will be changing in frequency and apparantly not sync'd.

Just some food for thought.
Any help ?, yes no let me know.

Regards

 

[melone]

Laffalot,

VERY interesting idea. I am not exactly sure that I can implement it due to availability of the control signals, but I see where you are going with it. I want to do a little number crunching and see if the delay through the divide by N stage is acceptable.

The only other problem that I see is the higher clock frequency. By increasing the master clock frequency, I am dumping more energy into the clock line. This will cause the problem frequencies (due to the harmonics) to increase if I am not careful on how much I increase the frequency. I am just concerned about fixing one problem and creating a couple more (due to the peak RF emmisions at the harmonics of the new higher frequency clock).

Thanks for the very unique solution. I will keep you posted on any progress that is made!

Thanks again to all!

 

[MMAshwin]

Hi again,

Another thought came to me as I read your last post.

Instead then, of a higher master clock you could use a low one and double/tripple/quadruple etc the clock at the appropriate ICs.

A simple clock doubler could be a monostable which is triggered by the rising & falling edge of the slow master clock. How long the clock pulse last depends on your settings for the monostable.

Just a quick example of what I mean.

____----____----____----____----____----____---- 1 Mhz Clk
____--__--__--__--__--__--__--__--__--__--__--__ x2a
____-___-___-___-___-___-___-___-___-___-___-___ x2b
____-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-x4

In the x2a waveform the pulse width from the monostable is symetrical, where as in x2b the pulse width of the clock is set to the same pulse width as the x4 clock.

So you take a slow clock as your master, double it, the output of which you feed into another doubler & so on.
The pulse duration is set by you and can be different for each stage of the doubling proceedure.

As your master clock is lower, then there will be less RF radiation across the main PCB run. Keep the doubling stages next to the relevent ICs which require sync.

How low you go with the master clock depends on how many multipliers you want at the remote end.

Just another thought.
Any help ?, yes no let me know.

Regards